In-cycle Resource Sharing for Microprocessor High-Level Synthesis
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Solution Overview
Problem
Current resource sharing techniques in microprocessor design are limited to temporal mutual exclusiveness, where resources are shared across multiple clock cycles, whereas in-cycle sharing is necessary for efficient high-level synthesis, particularly in pipelined designs where cycle behavior is fixed.
Innovation Solution
The method involves constructing a graph representing logical operations, assigning weights based on node differences, enumerating weighted cliques, and replacing these cliques with multiplexers to enable resource sharing within the same clock cycle, allowing for the sharing of resources among operations that do not conflict.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If current resource sharing techniques are used, then resources can be shared across multiple clock cycles, but resource sharing cannot occur within the same clock cycle
Solution Approach 1:
The invention segments the resource sharing problem into two distinct dimensions: temporal segmentation (across clock cycles) and spatial segmentation (within the same clock cycle). By constructing a conflict graph that identifies operations sharing the same resource within a cycle, the patent enables spatial segmentation of resource allocation, allowing multiple non-conflicting operations to share resources simultaneously without temporal overlap.
Solution Approach 2:
The patent transitions from one-dimensional temporal resource sharing to two-dimensional resource sharing by adding the spatial dimension (within-cycle sharing). The conflict graph approach enables operations to be shared across both time (different cycles) and space (same cycle, different operation instances), effectively utilizing the fourth dimension of resource allocation.
2Productivity
If more resources are allocated to operations, then operational capacity increases, but area consumption increases
Solution Approach 1:
The invention makes resources universal by enabling them to serve multiple operations within the same clock cycle, not just across different cycles. The conflict graph identifies operations that can share the same resource instance, allowing a single resource to perform multiple functions simultaneously for different operation instances, thereby reducing the total number of resources needed while maintaining operational capacity.
Solution Approach 2:
The patent merges multiple operation instances that share the same resource into a single resource allocation. By identifying operations with identical resource requirements through the conflict graph, the invention combines their resource demands into one shared resource, reducing area consumption while preserving the ability to execute all operations.
3Adaptability or versatility
If resources are shared across multiple clock cycles, then resource utilization improves, but timing constraints are more difficult to satisfy
Solution Approach 1:
The invention segments resource sharing into intra-cycle and inter-cycle components. By first identifying all operations that can share resources within the same cycle using the conflict graph, then handling inter-cycle sharing separately, the patent resolves timing constraints at each level independently, avoiding the complexity of simultaneous multi-cycle timing analysis.
Solution Approach 2:
The patent performs preliminary identification of within-cycle resource sharing opportunities using the conflict graph before finalizing the scheduling and binding process. This preliminary action captures all possible intra-cycle sharing scenarios, allowing the subsequent timing analysis to focus only on inter-cycle dependencies, thereby simplifying timing constraint satisfaction.
Data Source
AI summary
A graph is constructed, having a plurality of nodes representing a plurality of logical operations and a plurality of edges connecting those of the plurality of nodes which do not conflict. A weight, including a width difference between end nodes of each of the edges, is assigned to each edge. Weighted cliques are enumerated, each including at least two of the nodes. Each of the weighted cliques is replaced with a single one of the logical operations and a multiplexer, to obtain a plurality of multiplexer-operation groups, such that each logical operation in one of the multiplexer-operation groups can be shared within a same clock cycle of a digital electronic integrated circuit.