In-Device Polycrystalline Semiconductor for Parasitic Loss Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuit designs face challenges in reducing parasitic loss and harmonics, and achieving effective isolation between active device areas, particularly in bulk and semiconductor-on-insulator structures, where existing high-resistivity polycrystalline semiconductor elements are either buried or placed outside active device areas.
Innovation Solution
Incorporating one or more in-device high resistivity polycrystalline semiconductor elements within active semiconductor devices, such as field effect transistors, which extend vertically through monocrystalline portions, allowing for reduced parasitic loss, harmonics, and improved isolation by selectively placing these elements within the device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If high-resistivity polycrystalline semiconductor elements are buried within bulk semiconductor substrate or placed outside active device areas, then isolation between active device areas is achieved, but parasitic loss and harmonics cannot be effectively reduced within active device areas
Solution Approach 1:
The patent embeds polycrystalline semiconductor elements directly within the active device area, nesting them inside the semiconductor layer at specific locations such as source/drain regions. This allows the elements to be integrated within the active device structure rather than being separate buried or external elements, thereby reducing parasitic loss without significantly increasing overall device complexity
Solution Approach 2:
The patent applies different crystalline structures (monocrystalline vs. polycrystalline) at different local regions within the active device area. Specifically, polycrystalline portions are formed in source/drain regions while maintaining monocrystalline structure in channel regions, allowing targeted reduction of parasitic loss in specific areas while preserving device performance in other areas
2Object-affected harmful factors
If polycrystalline semiconductor elements are formed within active device areas, then parasitic loss and harmonics are reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent incorporates polycrystalline semiconductor elements during the initial formation of the semiconductor layer, before active device fabrication begins. By pre-forming the semiconductor layer with embedded polycrystalline portions at desired locations, the need for additional processing steps to create separate polycrystalline elements is eliminated, and these elements are already in place to reduce parasitic loss in subsequent device fabrication
Solution Approach 2:
The patent combines the formation of the semiconductor layer with the creation of polycrystalline elements, merging two separate manufacturing processes into one. The semiconductor layer is formed with embedded polycrystalline portions using a single continuous process rather than requiring separate steps for layer formation and element insertion, thereby simplifying manufacturing while achieving parasitic loss reduction
Data Source
AI summary
Disclosed is a structure including a semiconductor layer with a device area and, within the device area, a monocrystalline portion and polycrystalline portion(s) that extend through the monocrystalline portion. The structure includes an active device including a device component, which is in device area and which includes polycrystalline portion(s). For example, the device can be a field effect transistor (FET) (e.g., a simple FET or a multi-finger FET for a low noise amplifier or RF switch) with at least one source/drain region, which is in the device area and which includes at least one polycrystalline portion that extends through the monocrystalline portion. The embodiments can vary with regard to the type of structure (e.g., bulk or SOI), with regard to the type of device therein, and also with regard to the number, size, shape, location, orientation, etc. of the polycrystalline portion(s). Also disclosed is a method for forming the structure.