In-DRAM Error Correction Circuit Fail Bit Generation
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Solution Overview
Problem
The increasing operating speed of semiconductor memory devices leads to higher error probabilities, necessitating effective error correction methods without significantly increasing manufacturing costs, as existing solutions require additional parity codes and detection codes that inflate costs.
Innovation Solution
A memory module and controller system that includes dynamic random access memory (DRAM) chips with in-DRAM error correction circuits generating fail bits for intra-chip error detection, allowing for error correction without a separate detection code, and a buffer or control chip to manage fail information and recover data from failed chips using parity codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory controller generates parity codes and stores them in semiconductor memory devices to correct errors, then error correction capability is improved, but the number of memory chips increases and manufacturing cost increases
Solution Approach 1:
The patent merges the error detection function into the existing parity code structure by using fail bits generated from parity check results. Instead of requiring separate detection codes and parity codes, the system combines both functions into a single parity code mechanism, where the same parity code used for error correction also enables error detection through fail bit generation.
Solution Approach 2:
The patent extracts the error detection function from the traditional separate detection code structure and integrates it into the parity code system. By generating fail bits directly from parity check results, the system removes the need for dedicated detection code storage while maintaining both detection and correction capabilities.
2Measurement precision
If separate detection codes are stored in memory chips to identify failed chips, then error detection precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent makes the parity code multi-functional by using it for both error detection and error correction. The fail bits generated from parity check results serve dual purposes: indicating detection status and enabling identification of failed chips for correction operations, eliminating the need for separate detection code structures.
Solution Approach 2:
The system uses the existing parity code mechanism to serve the error detection function without requiring additional dedicated detection codes. The parity check process itself generates fail bits that automatically provide detection information, making the system self-sufficient for both detection and correction functions.
Data Source
AI summary
A memory module for reporting information about a fail in chip units, an operation of a memory module, and an operation of a memory controller are provided. The memory module includes: first to Mth memory chips (where M is an integer that is equal to or greater than 2) mounted on a module board and storing data, and an (M+1)th memory chip mounted on the module board and storing a parity code for recovering data of a memory chip in which a fail in chip units occurs among the first to Mth memory chips, wherein fail bits are generated from the first to (M+1)th memory chips through an intra-chip error detection operation, and fail information is output according to a result of calculating the fail bits from the first to (M+1)th memory chips.