In-Fab Wafer Yield Prediction Using Virtual Process Paths

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Solution Overview

Problem

Current methods for predicting the yield of in-fab wafers are inaccurate due to the inability to predict yields at the wafer unit level and the failure to consider processed and measured data for each wafer.

Innovation Solution

A method involving the generation of a virtual process path using data corresponding to the residual process of an in-fab wafer, combined with a yield predicting model trained with supervised learning from wafer data of fab-out wafers, to predict the yield of the in-fab wafer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If yield prediction is performed in LOT units using added or subtracted yield-related factors, then the prediction process is simple, but the prediction accuracy is low and wafer-unit level prediction is impossible

Engineering Contradiction:
Improveprediction process complexityVSAvoidyield prediction accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent segments the yield prediction from LOT-level aggregation to wafer-unit-level individual prediction. Each wafer is processed independently through the neural network model, allowing individual yield assessment rather than batch-level estimation. This segmentation enables tracking of specific wafer characteristics and their impact on yield.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a neural network model as an intermediary between raw wafer data and yield prediction results. This intermediary component processes complex relationships between multiple process parameters and yields, transforming structured wafer data into accurate yield predictions at the wafer-unit level.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If processed data and measured data of each wafer are not considered in yield prediction, then the prediction method is simple, but the accuracy of yield prediction is low

Engineering Contradiction:
Improvedata processing complexityVSAvoidyield prediction accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent performs preliminary actions by collecting and organizing wafer data from multiple process stages before yield prediction. Process data, measurement data, and inspection data are gathered and pre-processed in advance, creating a comprehensive dataset that feeds into the neural network model for accurate yield prediction.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The neural network model serves multiple functions: it processes diverse data types (process parameters, measurement values, inspection results), handles different wafer stages, and outputs yield predictions. This multi-functional approach consolidates various data processing tasks into a single unified system.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250148174A1Method and device with in-fab wafer yield prediction
Publication Date: 2025.05.08 SAMSUNG ELECTRONICS CO LTD
  • US20250148174A1 patent drawing
  • US20250148174A1 patent drawing
  • US20250148174A1 patent drawing

AI summary

A method and a device for predicting a yield of an in-fab wafer including: generating at least one virtual process path on a residual process of the in-fab wafer; and predicting the yield of a virtual fab-out wafer that corresponds to the at least one virtual process path by using a trained yield predicting model are provided.