3D Emulation of In-Kerf Optical Macros for Wafer Design
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Solution Overview
Problem
As technology nodes shrink, the frame design layout validation process becomes increasingly challenging due to issues with in-kerf optical macros, where actual structures often deviate from design predictions, leading to costly and time-consuming iterative redesigns.
Innovation Solution
A computer-aided design (CAD) system employing a three-dimensional (3D) emulator for preliminary verification of in-kerf optical macros, allowing for the generation of 3D images at different process steps and comparison with predicted structures, enabling alterations to the macro design or process flow to ensure accurate formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional wafer-level design layout verification is performed without 3D emulation, then the verification process is simpler and faster, but the accuracy of predicting in-kerf optical macro structures deteriorates, leading to validation failures
Solution Approach 1:
The patent applies preliminary action by performing 3D emulation of in-kerf optical macros during the design verification stage, before actual wafer fabrication. This allows the predicted structure to be compared with the emulated structure in advance, identifying potential validation failures and enabling design corrections before manufacturing, thereby improving prediction accuracy without compromising the overall process efficiency
Solution Approach 2:
The patent uses 3D emulation to create a virtual copy of the in-kerf optical macro structure formation process. This digital replica allows for accurate prediction and comparison of macro structures at different process steps, enabling high-precision verification without requiring physical prototypes or test wafers, thus improving measurement precision while managing complexity through virtual simulation
2Quantity of substance
If technology node scaling is pursued to improve chip density, then chip capacity increases, but the validation of frame design layouts becomes more difficult due to deviations in in-kerf optical macro structures
Solution Approach 1:
The patent performs preliminary 3D emulation and comparison of in-kerf optical macro structures at different process steps before actual fabrication. This allows identification and correction of validation issues arising from technology node scaling effects, ensuring that frame design layouts are optimized for the specific process conditions before manufacturing, thereby maintaining validation reliability as technology nodes scale
Solution Approach 2:
The patent implements a feedback mechanism where the predicted macro structure is compared with the emulated macro structure at multiple process steps. This comparison provides feedback on deviations caused by technology node scaling, allowing for iterative design adjustments and process optimization, ensuring that frame design layouts remain reliable even as technology nodes shrink and chip density increases
3Manufacturing precision
If iterative redesign processes are performed to correct in-kerf optical macro deviations, then the accuracy of macro structure formation improves, but the manufacturing time and cost increase
Solution Approach 1:
The patent performs preliminary verification using 3D emulation during the design stage, identifying and correcting macro structure formation issues before actual manufacturing. This upfront verification prevents the need for costly and time-consuming iterative redesign cycles during production, as potential problems are resolved in the virtual simulation phase, thereby achieving high manufacturing precision without significant time loss
Solution Approach 2:
The patent uses 3D emulation to create virtual models of the macro structure formation process, allowing for accurate prediction and optimization of manufacturing outcomes. This virtual copying enables multiple design iterations and optimizations to be performed digitally rather than physically, achieving high manufacturing precision through virtual prototyping while minimizing the time and material costs associated with physical iterative redesign
Data Source
AI summary
Disclosed are embodiments of a system, method and computer program product for wafer-level design including chip and frame design. The embodiments employ three-dimensional (3D) emulation to preliminarily verify in-kerf optical macros included in a frame design layout. Specifically, 3D images of a given in-kerf optical macro at different process steps are generated by a 3D emulator and a determination is made as to whether or not that macro will be formed as predicted. If not, the plan for the macro is altered using an iterative design process. Once the in-kerf optical macros within the frame design layout have been preliminarily verified, wafer-level design layout verification, including chip and frame design layout verification, is performed. Once the wafer-level design layout has been verified, wafer-level design layout validation, including chip and frame design layout validation, is performed. Optionally, an emulation library can store results of 3D emulation processes for future use.