In-Line Interconnect Test Circuit for IC Electrical Property Measurement
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Solution Overview
Problem
Current methods for testing the electrical properties of interconnects in integrated circuits (ICs) require removing ICs from the production line, are costly, and involve measuring cross-sectional areas or properties directly, which is inefficient and increases production complexity.
Innovation Solution
An in-line test circuit with a gate chain and ring path that includes underlying and overlying test segments, allowing for the determination of electrical properties without removing the IC from the production line, by activating logic circuitry to substitute test segments in the ring path after each interconnect layer is formed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dedicated test equipment with test probes is used to directly measure interconnect properties, then measurement precision is improved, but device complexity and loss of time increase due to removing ICs from production line
Solution Approach 1:
Test segments are pre-integrated into the interconnect layers during fabrication, and the test circuit is built into the IC before final assembly. This allows testing to be performed in-line without removing the IC from the production line, eliminating production downtime while maintaining measurement capability
Solution Approach 2:
A test circuit with ring oscillator and logic circuitry serves as an intermediary system that enables electrical property measurement through standard production line equipment rather than requiring dedicated test probes. The test circuit converts physical interconnect properties into measurable electrical signals that can be assessed using existing production infrastructure
2Measurement precision
If multiple interconnect layers are tested using traditional methods, then measurement precision is improved, but loss of time and device complexity increase due to multiple trips to test station
Solution Approach 1:
Test segments are pre-integrated into multiple interconnect layers during fabrication, enabling all layers to be tested in a single in-line operation rather than requiring multiple separate trips to test stations, thus maintaining measurement precision while dramatically improving productivity
Solution Approach 2:
The test circuit combines multiple test segments from different interconnect layers into a single integrated testing system. The ring oscillator can sequentially or simultaneously evaluate multiple layers through shared circuitry, consolidating what would traditionally require multiple separate testing operations into one unified process
3Reliability
If test circuit is replicated at several locations within IC, then reliability is improved, but area of stationary object increases
Solution Approach 1:
The test circuit is divided into modular components distributed across different interconnect layers. Test segments are embedded within specific interconnect layers while sharing common circuit elements (such as the ring oscillator and logic circuitry), allowing multiple testing locations without proportionally increasing total area
Solution Approach 2:
The ring oscillator and associated logic circuitry serve multiple functions: they can test different interconnect layers sequentially, evaluate various electrical properties (resistance, capacitance, delay), and operate with different test segment configurations. This multi-functionality reduces the need for separate dedicated test circuits for each layer or property
Data Source
AI summary
A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating the test circuit or the method. In one embodiment, the test circuit includes a gate chain having a ring path and a stage. In one embodiment, the stage includes: (1) a underlying test segment in the underlying interconnect layer, (2) a overlying test segment in the overlying interconnect layer and (3) logic circuitry activatible after formation of the underlying interconnect layer and before formation of the overlying interconnect layer to place the underlying test segment in the ring path and further activatible after the formation of the overlying interconnect layer to substitute the overlying test segment for the underlying test segment in the ring path.