In-Memory Arithmetic Circuit for Faster Integer Operations
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Solution Overview
Problem
Conventional cache memory is limited by slow read and write operations, leading to increased memory burden as data requirements grow, and existing in-memory computing structures face bottlenecks in performing arithmetic operations efficiently.
Innovation Solution
An in-memory computing device with a memory cell array and column peripheral circuit that includes sense amplifying and writing units, arithmetic logic units with full adder Boolean equations, and a shift register circuit to perform high-speed integer operations, reducing carry propagation delay and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional cache memory is used for read and write operations, then the memory structure is simple, but the operation speed is slow
Solution Approach 1:
The patent merges memory storage function with arithmetic computation function into a single in-memory computing device. The memory cell array stores data while the column peripheral circuit performs arithmetic operations directly on the stored data, eliminating the need for separate memory and processor units, thus improving operation speed without excessive complexity increase
Solution Approach 2:
The column peripheral circuit is designed to perform multiple functions including sense amplifying, arithmetic operations (addition, subtraction, multiplication, division), and write back operations. This multi-functional design allows the same hardware structure to handle both memory operations and computational tasks, improving overall system speed
2Speed
If arithmetic operations are performed in memory, then operation speed improves, but carry propagation delay increases
Solution Approach 1:
The arithmetic operations are segmented into multiple stages using pipeline architecture. The column peripheral circuit is divided into sense amplifying unit, arithmetic logic unit, and write back unit that operate in parallel stages. This segmentation allows carry propagation to occur in parallel across different bit positions rather than sequentially, significantly reducing carry propagation delay
Solution Approach 2:
The patent transitions from sequential carry propagation (one-bit-at-a-time) to parallel carry propagation by implementing full adder circuits that handle multiple bits simultaneously. The column peripheral circuit processes multiple data bits in parallel across different word lines, adding a dimensional aspect to the computation that reduces time delay
3Productivity
If in-memory computing is implemented, then arithmetic operation capability is added, but energy consumption increases
Solution Approach 1:
The memory cell array performs arithmetic operations on data already stored within it, eliminating the need to move data between memory and processor. The computation is self-service in that it occurs in-situ where the data resides, reducing energy consumption associated with data transfer and external processing
Solution Approach 2:
By merging storage and computation functions into a single device, the patent eliminates energy-wasting data movement between separate memory and processor units. The column peripheral circuit performs arithmetic operations directly on stored data, reducing overall system energy consumption despite adding computational functionality
Data Source
AI summary
An in-memory computing device includes a memory cell array and a column peripheral circuit including a plurality of column peripheral units connected to a plurality of pairs of bit lines connected to the memory cell array. Each of the column peripheral units includes a sense amplifying and writing unit sensing and amplifying bitwise data through one pair of bit lines among the pairs of bit lines and an arithmetic logic unit performing an arithmetic operation with a full adder Boolean equation based on the bitwise data and performing a write back operation on operation data obtained by the arithmetic operation via the sense amplifying and writing unit.