In-Memory Checksum Cells for Error Detection and Correction
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Solution Overview
Problem
Existing in-memory computing systems lack effective mechanisms for error detection and correction during linear operations, such as multiply and accumulate (MAC) arithmetic operations, which are crucial for tasks like neural network computations, leading to potential inaccuracies and reliability issues.
Innovation Solution
A checksum mechanism is implemented in hardware to detect and correct errors in in-memory computations by utilizing memory cells with specific resistances that form a checksum comparable to the sum of the resistances of other memory cells, allowing for error detection and correction through comparisons and adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware lockstep duplication is used for error detection, then reliability is improved, but device complexity and resource consumption increase significantly
Solution Approach 1:
The patent extracts only the essential checksum computation function from the full compute resources, separating error detection from the main computation. By taking out only the necessary checksum memory cells and resistance values, the system achieves error detection without duplicating entire compute resources, thus resolving the contradiction between reliability and device complexity.
Solution Approach 2:
The patent introduces checksum memory cells as intermediary elements that mediate between the main compute resources and the error detection function. These intermediary checksum cells with specific resistance values enable error detection without requiring direct duplication of the main compute resources, allowing the system to maintain reliability while reducing overall device complexity.
2Reliability
If checksum mechanism with additional memory cells is implemented, then error detection reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the checksum function with the existing memory cell structure by using the same physical memory cells to store both compute data and checksum values. The checksum memory cells are integrated into the existing memory array, sharing the same physical infrastructure, which reduces device complexity while maintaining error detection reliability.
Solution Approach 2:
The patent makes the memory cells universal by enabling them to serve multiple functions: storing compute data, storing checksum values, and performing both computation and error detection. This multi-functionality eliminates the need for separate dedicated checksum hardware, reducing device complexity while preserving error detection capabilities.
3Manufacturing precision
If resistance-based checksum is used, then manufacturing precision requirements are reduced, but measurement precision for error detection must be maintained
Solution Approach 1:
The patent applies self-service by using the memory cells' inherent resistance values to automatically generate checksum outputs that inherently account for manufacturing variations. The checksum computation uses the same resistance-based mechanism as the main computation, so both outputs are affected equally by manufacturing tolerances, allowing error detection without requiring high manufacturing precision while maintaining measurement precision for detection purposes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides reliable error detection and correction for in-memory computations, ensuring accurate results in linear operations like MAC arithmetic operations, particularly in neural networks, by leveraging the linearity of these operations with minimal overhead.
Implementation Method 1
a respective memory cell in the set of memory cells comprises a respective resistance, wherein the device comprises the set of memory cells and at least one memory cell, in particular at least two memory cells, for determining a checksum, that comprises a resistance that is the same or essentially the same as the sum of the respective resistances
Data Source
AI summary
A method and a device for error detection, in particular for error correction, in in-memory computations with a set of memory cells for determining a result of a linear operation. Each respective memory cell in the set of memory cells includes a respective resistance. The device includes the set of memory cells and a memory cell for determining a checksum, that includes a resistance that is the same or essentially the same as the sum of the respective resistances.