In-Memory Computation Circuit with Compensation Memory Cell String

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Solution Overview

Problem

Existing in-memory computation devices face challenges in accurately performing multiply-accumulate (MAC) computations due to weight values with peak values of 0 and non-0, requiring effective storage and compensation methods to ensure stable operation and accuracy.

Innovation Solution

An in-memory computation device with a memory cell array, compensation memory cell string, and operator that sets peak weight values to 0 and compensates computations by multiplying signals with peak weight information, ensuring stable operation and accurate results without affecting MAC computation correctness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If weight values with peak value 0 are stored in memory cells for stable operation, then operational stability is improved, but computation accuracy deteriorates due to inability to represent non-zero peak weight distributions

Engineering Contradiction:
Improveoperational stabilityVSAvoidcomputation accuracy
Core Design Contradiction:
Stability of the object's compositionVSMeasurement precision

Solution Approach 1:

The patent segments the weight representation into two parts: the memory cell array stores weights with peak value 0 for stable operation, while a separate compensation mechanism (additional memory cells or offset values) stores the peak weight information. This segmentation allows each component to fulfill its specific function without compromise.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a compensation mechanism as an intermediary element that bridges the gap between the simplified 0-peaked weights stored in memory and the actual non-zero peak weight distributions required for accurate computation. This intermediary compensates for the representation error introduced by the stable but simplified weight storage scheme.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If compensation mechanisms are added to improve computation accuracy, then accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvecomputation accuracyVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the parameter representation by storing weights with peak value 0 in the main memory array and using separate compensation values (offsets) to represent the actual peak weights. This parameter transformation allows the system to maintain stable memory operation while achieving accurate computation through parameter compensation rather than complex structural modifications.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If peak weight values are set to 0 for stable memory operation, then operational reliability is improved, but information representation capability deteriorates

Engineering Contradiction:
Improveoperational reliabilityVSAvoidweight distribution information
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The patent extracts the peak weight information from the main weight storage and places it in a separate compensation structure. This extraction allows the memory cells to focus on storing stable 0-peaked weights while the extracted peak information is preserved separately and applied during computation to recover the full weight distribution information.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS12198766B2Artificial neural network operation circuit and in-memory computation device thereof
Publication Date: 2025.01.14 MACRONIX INTERNATIONAL CO LTD
  • US12198766B2 patent drawing
  • US12198766B2 patent drawing
  • US12198766B2 patent drawing

AI summary

An artificial neural network operation circuit and an in-memory computation device of the artificial neural network operation circuit are proposed. The in-memory computation device includes a memory cell array, a compensation memory cell string, and an operator. The memory cell array has a plurality of memory cells to store a plurality of weight values. The memory cell array has a plurality of word lines and a plurality of bit lines. Each compensation memory cell of the compensation memory cell string stores a unit weight value. The operator multiplies a signal on a compensation bit line by peak weight information of the weight values to generate a first signal and adds the first signal to each signal on the bit lines to obtain a plurality of computation results, respectively.