In-Memory Computation Device with Configurable Data Routing
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Solution Overview
Problem
The efficient movement of data among synaptic layers in neural networks is a time-consuming process due to the large number of neurons involved, which hampers the execution of neural network operations in in-memory computing devices.
Innovation Solution
An in-memory computation device is designed with a memory configuration of blocks, each equipped with page input and output circuits, a data bus system, and bit line bias circuits, allowing for configurable data routing and efficient data transfer between blocks and external sources, enabling various neural network configurations and operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is moved among synaptic layers using conventional routing methods, then neural network operations can be executed, but the process becomes time-consuming due to the large number of neurons involved
Solution Approach 1:
The memory is divided into multiple blocks, each with dedicated page input and output circuits. This segmentation allows parallel data access and transfer operations across different blocks, significantly improving data movement speed and reducing execution time for neural network operations involving large numbers of neurons.
Solution Approach 2:
Page input circuits and page output circuits are introduced as intermediary components between the memory blocks and the computational units. These intermediary circuits buffer and manage data flow, enabling efficient data transfer without becoming a bottleneck, thus improving speed while reducing time loss.
2Productivity
If memory is configured with multiple blocks and page circuits for efficient data transfer, then data movement efficiency improves, but device complexity increases
Solution Approach 1:
The page input circuits and page output circuits are designed to serve multiple blocks and support various neural network configurations. These universal circuits can be dynamically configured through control signals to handle different data routing requirements, improving productivity while managing complexity through reuse rather than duplication.
Solution Approach 2:
The memory system incorporates dynamic configuration capabilities where page circuits can be reconfigured between sensing cycles or in longer intervals to support different neural network architectures. This dynamic adaptability allows the system to optimize for specific workloads, improving productivity without permanently increasing structural complexity.
Data Source
AI summary
An in-memory computation device is described that comprises a memory with a plurality of blocks B(n) of cells, where n ranges from 0 to N−1. A page output circuit PO(n) and page input circuit PI(n) are operatively coupled to block B(n) in the plurality of sets. A data bus system for providing an external source of input data and a destination for output data is provided. Data circuits are configurable connect page input circuit PI(n) to one or more of page output circuit PO(n), page output circuit PO(n−1), and the data bus system to source the page input data in a sensing cycle. This configuration can be done between each sensing cycle, or in longer intervals, in order to support a variety of neural network configurations and operations.