In-Memory Computation Device with Segmented Memory Tiles
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Solution Overview
Problem
In-memory computation devices face significant challenges in reducing data storage demand and power consumption, particularly in large-scale multiply-add operations for deep neural networks, which are essential for AIoT applications.
Innovation Solution
The device divides the memory array into p×q memory tiles with bit line selection switches and analog-to-digital converters (ADCs) to generate sub-output signals, which are then processed by a ladder adder for calculation, allowing for adjustable bit numbers and reduced data storage needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large-scale memory array is used for multiply-add operations in deep neural networks, then computation capability is improved, but data storage demand and power consumption increase significantly
Solution Approach 1:
The memory array is divided into multiple sub-memory arrays, each handling a portion of the multiply-add operations. This segmentation allows the system to process large-scale computations while using smaller, more manageable memory units, thereby reducing the data storage demand of any single memory unit while maintaining overall computation capability.
Solution Approach 2:
The patent introduces a third dimension by stacking multiple sub-memory arrays vertically. This 3D architecture enables the system to perform large-scale multiply-add operations across multiple layers, effectively increasing computation capability without proportionally increasing the data storage demand in any single layer.
2Productivity
If a large-scale memory array is used for multiply-add operations, then computation capability is improved, but power consumption increases
Solution Approach 1:
By dividing the memory array into multiple sub-memory arrays, the total power consumption is distributed across multiple smaller units. Each sub-memory array consumes less power individually, and the segmented architecture allows for more efficient power management while maintaining high computation capability through parallel operations.
Solution Approach 2:
The vertical stacking of sub-memory arrays in 3D enables computation to be distributed across multiple layers, reducing the power consumption burden on any single layer while maintaining high overall computation capability through layered parallel processing.
3Quantity of substance
If the memory array is divided into multiple memory tiles with bit line selection switches, then data storage demand is reduced, but device complexity increases
Solution Approach 1:
The bit line selection switches are designed to serve multiple functions: they select which bit lines are active for computation, enable or disable specific memory tiles, and control the flow of data between sub-memory arrays. This multi-functionality reduces the need for separate control mechanisms, thereby managing device complexity while enabling data storage reduction through selective activation.
Solution Approach 2:
The bit line selection switches provide dynamic control over the active memory tiles and bit lines based on computation requirements. This dynamic configuration allows the system to adaptively reduce data storage demand by activating only the necessary memory portions, while the reconfigurability manages complexity through software-controlled flexibility rather than hardwired complexity.
Data Source
AI summary
An in-memory computation device including a memory array, p×q analog to digital converters (ADCs) and a ladder adder is provided. The memory array is divided into p×q memory tiles, where p and q are positive integers larger than 1. Each of the memory tiles has a plurality local bit lines coupled to a global bit line respectively through a plurality of bit line selection switches. The bit line selection switches are turned on or cur off according to a plurality of control signals. The memory array receives a plurality of input signals. The ADCs are respectively coupled to a plurality of global bit lines of the memory tiles. The ADCs respectively convert electrical signals on the global bit lines to generate a plurality of sub-output signals. The ladder adder is coupled to the ADCs, and performs an addition operation on the sub-output signals to generate a calculation result.