In-Memory Computing Circuit Parallel Processing
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Solution Overview
Problem
Conventional in-memory computing solutions are inefficient for big data processing, particularly in neural network applications, due to serial processing methods that increase energy consumption and processing times, and require additional non-volatile memory, leading to cost and size increases, and are not adaptable to different memory cuts.
Innovation Solution
A memory device with a computing circuit that performs parallel big data processing by utilizing existing memory cells and bit lines, featuring a biasing stage and combining stage to generate an output electric quantity indicative of a linear combination of input electric quantities, allowing for easy integration with existing memory devices without significant circuit complexity or additional memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial processing by controllers is used for in-memory computing, then data processing can be performed, but energy consumption and processing times significantly increase
Solution Approach 1:
The patent replaces the mechanical/control-based serial processing system with an electrical parallel processing system. By utilizing the inherent electrical properties of memory cells (resistance, conductance) and applying Kirchhoff's laws, the system performs matrix operations through simultaneous electrical signal interactions across multiple memory cells, eliminating the sequential bottlenecks of controller-based processing
Solution Approach 2:
The patent transitions from one-dimensional serial processing through controllers to two-dimensional parallel processing by exploiting the spatial arrangement of memory cells in rows and columns. Multiple computations occur simultaneously across different spatial locations in the memory array, with bit lines and word lines enabling concurrent operations across multiple cells
2Quantity of substance
If additional non-volatile memory is used to store processing parameters, then neural network parameters can be stored, but cost and size increase
Solution Approach 1:
The patent makes the memory device universally functional by enabling it to serve dual purposes: traditional data storage and in-memory computing operations. The same memory cells that store data also store neural network parameters and perform computational operations, eliminating the need for separate dedicated storage resources for processing parameters
Solution Approach 2:
The patent merges the storage function and computing function into a single integrated system. Neural network parameters are stored directly in the memory cells alongside data, and the same electrical circuits used for data retrieval are also used for computational operations, combining previously separate functions into one unified device
3Adaptability or versatility
If conventional in-memory computing solutions are used, then data processing can be performed, but they are not adaptable to different memory cuts
Solution Approach 1:
The patent introduces dynamic configurability to the memory device by enabling runtime selection and reconfiguration of computational parameters such as scaling factors, offset values, and active memory cell regions. This dynamic adaptation allows the same hardware to be reconfigured for different memory cuts and application requirements without physical redesign
Solution Approach 2:
The patent enables adaptability through parameter changes in the control logic and computation parameters. By modifying control signals, selection criteria, and computational parameters (scaling factors, offsets), the system adapts to different memory cuts and configurations without changing the physical hardware structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces energy consumption and processing times for big data processing, eliminates the need for additional non-volatile memory, and enables efficient matrix processing in neural network applications while being adaptable to various memory cuts.
Implementation Method 1
each memory cell is configured to store data using phase change materials (such as chalcogenide) capable of stably transitioning between amorphous and crystalline phases according to an amount of heat transferred thereto
Implementation Method 2
The amorphous and crystalline phases exhibit different resistance values, (or, equivalently, transconductance values) which are used to distinguish different logic states of the memory cell
Data Source
AI summary
An embodiment memory device comprises a plurality of memory cells, each exhibiting a transconductance depending on a value of a stored bit, a plurality of bit lines associated with respective groups of memory cells, each bit line configured to flow a respective electric current indicative of the bit stored in a selected memory cell of the respective group of memory cells, and a computing circuit providing an output electric quantity indicative of a linear combination of a plurality of input electric quantities. The computing circuit comprises a biasing stage configured to bias each bit line with a respective input electric quantity, the electric current flowing through each bit line based on a product of the respective input electric quantity and the transconductance of the selected memory cell, and a combining stage for combining the electric currents flowing through the plurality of bit lines thereby obtaining the output electric quantity.