In-Memory Computing Circuit for Neural Network Processing

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Solution Overview

Problem

Current neural network processing methods require extensive computation and energy due to frequent data movements between memory and arithmetic units in Von Neumann architecture, limiting performance and efficiency in machine learning and inferencing tasks.

Innovation Solution

An in-memory computing (IMC) circuit that integrates memory banks with logic operations, using NAND gates and transistors to perform multiply-accumulate operations directly within memory, reducing the need for data transfer and enhancing processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If Von Neumann architecture is used for neural network processing, then data can be stored in memory, but frequent data movements between memory and arithmetic units cause high energy consumption and limit processing performance

Engineering Contradiction:
Improveenergy consumptionVSAvoidprocessing performance
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent merges memory storage and arithmetic computation into a single integrated unit. Each memory bank contains both weight storage capability and computation capability, allowing MAC operations to be performed directly within memory without transferring data to separate arithmetic units. This integration eliminates the energy-consuming data movement between memory and arithmetic units while maintaining high processing performance.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The memory bank is designed with multi-functionality, serving both as a storage unit for weight values and as a computation unit for performing MAC operations. The operator within each memory bank can process input values against stored weight values, making the memory system universally capable of both data retention and computational tasks, thereby reducing the need for separate processing components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If data movements between memory and arithmetic units are performed frequently, then computation can be executed, but processing efficiency is limited due to the overhead of data transfer

Engineering Contradiction:
Improveprocessing efficiencyVSAvoiddata transfer time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

By combining storage and computation functions within the same memory bank, the patent eliminates the time-consuming data transfer process. The operator within the memory bank performs MAC operations locally on data without requiring communication with external arithmetic units, thereby reducing processing time and improving overall efficiency.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If traditional Von Neumann architecture is used, then separate memory and arithmetic units can be implemented, but the architecture cannot accelerate matrix operations and MAC processes effectively

Engineering Contradiction:
Improvematrix operation speedVSAvoidsystem architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent accelerates matrix operations by performing MAC computations directly within the memory banks rather than requiring separate arithmetic units. This approach speeds up processing by eliminating data transfer bottlenecks while managing system complexity through a modular architecture where each memory bank is self-contained with integrated operator functionality.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP4332751A1Apparatus and method with in-memory computing (IMC)
Publication Date: 2024.03.06 SAMSUNG ELECTRONICS CO LTD
  • EP4332751A1 patent drawingFigure 1
  • EP4332751A1 patent drawingFigure 2A
  • EP4332751A1 patent drawingFigure 2B

AI summary

An apparatus and method with in-memory computing (IMC) are provided. An in-memory computing (IMC) circuit includes a plurality of memory banks, each memory bank including a bit cell configured to store a weight value and an operator configured to receive an input value, the operator being connected to the bit cell such that the operator upon receiving the input value outputs a logic operation result between the input value and the weight value, and a logic gate configured to receive the logic operation result of each of the memory banks.