In-Memory Computing Memory Array Using Floating Gate Transistors
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Solution Overview
Problem
Conventional computing architectures face challenges in meeting the extensive computational loads of deep neural networks due to low-bandwidth and high latency data communication with off-chip memory, necessitating innovative neural integrated circuits for non-Von Neumann computing architectures.
Innovation Solution
A computation architecture that exploits the physical attributes of a memory module to perform computations, using electrically programmable non-volatile memory cells and floating gate transistors to perform matrix-vector multiplication operations, reducing data transfer between the processor and memory by storing weights in memory cells and applying voltage pulses to multiply and sum inputs as analog signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional computing architecture is used with off-chip memory, then data storage capacity is sufficient, but data communication bandwidth is low and latency is high
Solution Approach 1:
The patent merges memory and computing functions by implementing in-memory computing architecture where neural network computations are performed directly within the memory array. This eliminates the need for data transfer between separate memory and processing units, thereby increasing data communication speed and computational throughput simultaneously.
Solution Approach 2:
The memory array is designed to serve multiple functions: data storage and neural network computation. By programming synaptic weights into the memory cells and applying input voltages, the same memory structure performs both storage and multiply-accumulate operations, improving overall system productivity.
2Adaptability or versatility
If more weight values are stored in memory cells, then neural network accuracy improves, but memory cell footprint increases
Solution Approach 1:
The patent uses conductance values of memory cells to represent synaptic weights, allowing a continuous range of weight values to be stored. By programming different conductance levels in the memory cells, a wide range of weight values can be represented without increasing the physical footprint of each memory cell, thus improving neural network accuracy while maintaining compact cell size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces energy consumption and latency, allows for a greater range of weight values without increasing memory cell footprint, and is applicable in neural network computing, enhancing the efficiency and scalability of memory modules.
Implementation Method 1
an electrically programmable non-volatile memory (NVM) programmed with a conductance value indicating a weight stored in the memory cell
Implementation Method 2
applying voltage pulses to multiply and sum inputs as analog signals
Implementation Method 3
each comprising a capacitor and an electrically programmable non-volatile memory (NVM) serially connected to the capacitor
Implementation Method 4
the weighted inputs are summed at the gate terminal, and an output signal is produced that represents the sum of the weighted inputs
Data Source
AI summary
A memory array, a memory structure and an operation method of a memory array are provided. The memory array includes memory cells, floating gate transistors, bit lines and word lines. The memory cells each comprise a capacitor and an electrically programmable non-volatile memory (NVM) serially connected to the capacitor, and further comprise a write transistor with a first source/drain terminal coupled to a common node of the capacitor and the electrically programmable NVM. The floating gate transistors respectively have a gate terminal electrically floated and coupled to the capacitors of a column of the memory cells. The bit lines respectively coupled to the electrically programmable NVMs of a row of the memory cells. The word lines respectively coupled to gate terminals of the write transistors in a row of the memory cells.