In-Memory Computing for Image Processing Efficiency
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Solution Overview
Problem
Existing technologies face inefficiencies in processing image data from image sensors, particularly in performing intensive computations like multiplication and accumulation, which are necessary for image segmentation, object recognition, and feature extraction.
Innovation Solution
The implementation of integrated circuit devices that include image sensing pixel arrays, memory cell arrays, and circuits to perform inference computations directly on the image data, utilizing hybrid bonding for efficient connectivity and enabling multiplication and accumulation operations within the memory cell arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If image data is transmitted from image sensors to general-purpose microprocessors for processing, then computation capability is provided, but processing efficiency deteriorates due to data transmission overhead and architectural mismatch
Solution Approach 1:
The patent merges the image sensor, memory cell array, and inference computation circuits into a single integrated circuit device. This consolidation eliminates the need for separate data transmission between components, as the memory cell array directly processes image data generated by the pixel array through in-situ multiplication and accumulation operations.
Solution Approach 2:
The patent transitions from a traditional von Neumann architecture (separating storage and processing) to a computing-in-memory architecture where computation is performed within the memory array itself. This dimensional shift in computational location enables parallel processing of image data without data movement overhead.
2Productivity
If specialized multiplier-accumulator circuits are implemented using memristor crossbar, then computation performance is improved, but device complexity increases
Solution Approach 1:
The memory cell array serves multiple functions: it stores weight values for neural network inference, performs multiplication operations through conductance modulation, and accumulates results through parallel current summation. This multi-functionality reduces the need for separate dedicated circuits for each operation.
Solution Approach 2:
The memory cell array performs computation autonomously using its inherent physical properties. The conductance of memory cells naturally implements multiplication when voltage is applied, and the parallel architecture automatically accumulates results through current summation, eliminating the need for external control logic for basic computational operations.
Data Source
AI summary
An integrated circuit device having a memory cell array with first layers of memory cells configured for operations of multiplication and accumulation. Each pair of closest layers among the first layers are configured to be separate by at least one layer in second layers of memory cells, where access to, or usages of, the second layers can be restricted or limited to prevent activities in the second layers from corrupting the weight programming in the first layers.