In-Memory Computing Circuit for Accelerated MAC Operations
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Solution Overview
Problem
Current in-memory computing (IMC) systems face challenges in efficiently performing multiply-accumulate (MAC) operations, which are crucial for machine learning and inferencing, due to the need for frequent data movement between memory and arithmetic units, leading to performance and power limitations.
Innovation Solution
The implementation of an IMC circuit with a plurality of memory banks, each containing a bit cell and an operator that performs logic operations, including NAND operations, and an adder to facilitate MAC operations directly within the memory, utilizing transistors to output signal results, and a controller to manage input values and clock signals across multiple devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is frequently moved between memory and arithmetic units for MAC operations, then computation can be performed, but performance and power efficiency deteriorate
Solution Approach 1:
The patent combines memory storage and computation operations into a single integrated structure. Memory banks contain bit cells that store weight values and simultaneously perform logic operations (NAND, AND) with input values. This merging eliminates the need for separate data movement between memory and arithmetic units, directly resolving the contradiction between computation performance and power consumption.
2Productivity
If data is frequently moved between memory and arithmetic units for MAC operations, then computation can be performed, but speed deteriorates
Solution Approach 1:
The integration of memory and computation units allows MAC operations to be performed in-place without data transfer delays. The logic gates (NAND gates) are directly connected to bit cells within memory banks, enabling immediate processing of stored weight values with input values, thereby significantly improving operation speed.
3Loss of energy
If logic operations are performed within memory banks using operators and logic gates, then data movement is reduced, but device complexity increases
Solution Approach 1:
The bit cells in memory banks are designed to serve multiple functions: storing weight values and performing logic operations. The operators connected to bit cells can perform various logic operations (NAND, AND) depending on the configuration of logic gates. This multi-functionality reduces the need for separate computation units while maintaining relatively simple circuit architecture.
Solution Approach 2:
The memory system is divided into multiple memory banks, each capable of independent logic operations. This segmentation allows parallel processing of different data sets while keeping each individual bank's circuit complexity manageable. Each bank contains bit cells, operators, and logic gates that work together as a self-contained computation unit.
Data Source
AI summary
An apparatus and method with in-memory computing (IMC) are provided. An in-memory computing (IMC) circuit includes a plurality of memory banks, each memory bank including a bit cell configured to store a weight value and an operator configured to receive an input value, the operator being connected to the bit cell such that the operator upon receiving the input value outputs a logic operation result between the input value and the weight value, and a logic gate configured to receive the logic operation result of each of the memory banks.