Configurable In-Memory Computing Array for Multi-Bit Matrix Operations
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Solution Overview
Problem
Conventional in-memory computing systems face inefficiencies in performing matrix-vector multiplications due to energy and delay costs associated with accessing data from memory, limiting energy/delay reductions and requiring separate memory and compute paradigms.
Innovation Solution
An in-memory computing architecture that includes a reshaping buffer, a compute-in-memory array, analog-to-digital converter circuitry, and control circuitry to perform multi-bit computing operations using single-bit internal circuits, enabling bit-parallel/bit-serial operations and near-memory computing to efficiently process multi-bit matrix and vector elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If separate memory and compute paradigms are used, then data storage and processing can be performed independently, but energy and delay costs increase due to data access between memory and compute units
Solution Approach 1:
The patent merges memory and compute functions into a unified compute-in-memory architecture where bit-cells perform both storage and computation operations. Matrix elements are stored in the memory array and multiplication with input vectors is performed directly within the bit-cells, eliminating the need to move data between separate memory and compute units, thereby reducing energy consumption and access delay.
Solution Approach 2:
The bit-cell architecture is designed to serve multiple functions: it stores matrix elements, performs multiplication operations with input vectors, and accumulates results. This multi-functional design allows the same hardware structure to handle both memory access and compute operations, reducing the overall system complexity despite the integrated functionality.
2Productivity
If multi-bit computing operations are performed using single-bit internal circuits, then computational efficiency is improved, but device complexity increases due to additional control circuitry
Solution Approach 1:
The patent segments multi-bit computing operations into multiple single-bit operations that are executed sequentially or in parallel across different bit-cells. Each bit-cell performs simple single-bit multiplication and accumulation, while the overall multi-bit result is obtained by combining these individual bit-level operations, thereby maintaining computational efficiency without requiring complex multi-bit circuits within each bit-cell.
Solution Approach 2:
The patent introduces control circuitry as an intermediary that manages and coordinates the single-bit operations to achieve multi-bit computing functionality. This control circuitry handles the sequencing, data routing, and result aggregation, allowing the bit-cells to remain simple while still achieving complex computational tasks through coordinated operation.
3Use of energy by moving object
If in-memory computing is implemented, then energy efficiency is improved, but adaptability decreases due to fixed architecture limitations
Solution Approach 1:
The patent implements dynamic configurability in the in-memory computing architecture, allowing the system to be reconfigured for different computational tasks and applications. The architecture supports programmability through configurable parameters such as matrix dimensions, computation modes, and data formats, enabling the same hardware to adapt to various workloads while maintaining energy-efficient in-memory computing operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables highly efficient linear algebra computations by reducing energy and delay costs, supporting programmability across various applications, and integrating with digital architectures for enhanced energy-proportional sparsity control and signal-to-quantization noise ratio management.
Implementation Method 1
compute operations within memory bit-cells provide their results as charge, typically using voltage-to-charge conversion via a capacitor
Implementation Method 2
bit-cell circuits involve appropriate switching of a local capacitor in a given bit-cell, where that local capacitor is also appropriately coupled to other bit-cell capacitors, to yield an aggregated compute result across the coupled bit-cells
Data Source
AI summary
Various embodiments comprise systems, methods, architectures, mechanisms or apparatus for providing programmable or pre-programmed in-memory computing operations.