In-Memory Computing Memory Cell for Low Power SRAM
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Solution Overview
Problem
Designing a stable and low-power SRAM architecture for in-memory computing has proven challenging due to issues with low-voltage cell instability and power consumption in existing solutions, particularly in digital MAC units and analog compute circuitry.
Innovation Solution
A memory cell with ten transistors is arranged to facilitate data storage and perform logical operations, including a first set of transistors for storing logic states and a second set of gate-coupled transistors that provide additional logic states and outputs, reducing vulnerability to data corruption and enabling high-density memory cell arrays with low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If digital MAC units are implemented in SRAM, then computational capability is improved, but power consumption increases due to full swing signal toggling
Solution Approach 1:
The patent changes the voltage swing parameter from full swing to small swing operations. The memory cell performs computational operations using small voltage swings instead of full swing signal toggling, thereby reducing power consumption while maintaining computational capability in SRAM-based MAC units
2Use of energy by moving object
If analog compute circuitry is added to SRAM, then power consumption is reduced, but array density decreases due to structural interruption
Solution Approach 1:
The patent merges the storage and compute functions into a unified memory cell structure. The same memory cell that stores data also performs computational operations through its transistor gate couplings, eliminating the need for separate analog compute circuitry and preserving SRAM array density while achieving low power consumption
3Device complexity
If eight transistor SRAM cell is used for in-memory computing, then integration is improved, but stability deteriorates due to low-voltage cell instability
Solution Approach 1:
The patent applies preliminary stabilization actions by designing the memory cell with specific transistor sizing ratios and coupling configurations that pre-establish stable operating conditions. The gate-coupled transistors are configured with appropriate size ratios to ensure stable low-voltage operation before computational operations begin, preventing instability issues
Data Source
AI summary
A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.