In-Memory Floating-Point Multiplication for One-Step IEEE 754 Compute
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Solution Overview
Problem
The existing Von Neumann computing architecture faces inefficiencies in floating-point multiplication operations due to the need for multiple steps of data manipulation and transportation, leading to increased power consumption and computational bottlenecks.
Innovation Solution
A binary floating-point in-memory multiplication device is designed to perform one-step floating-point multiplication by using two binary floating-point decoders, memory arrays for storing a base-2n multiplication code table, an adder circuit for exponent addition, and a binary floating-point encoder to convert the result into IEEE 754 format.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional Von Neumann architecture is used for floating-point multiplication, then the computation can be performed sequentially with standard instruction sets, but the computation efficiency is reduced and power consumption increases due to multiple manipulation steps and data transportation
Solution Approach 1:
The patent merges the storage function and computation function into a single integrated structure. The memory device stores multiplication tables and simultaneously performs multiplication operations by applying voltages to selected memory cells, eliminating the need for separate data transportation between storage and processing units. This combining of storage and computation directly addresses the Von Neumann bottleneck, improving computation efficiency while reducing power consumption associated with data movement.
Solution Approach 2:
The patent introduces voltage signals as an intermediary mechanism to perform computations directly within the memory device. By applying specific voltage patterns to memory cell word lines and bit lines, the system can retrieve and compute multiplication results without traditional data bus transportation. This voltage-based intermediary approach enables in-memory computing, reducing both the time and energy required for data manipulation and transportation.
2Productivity
If multiple steps of data manipulation and transportation are used in floating-point multiplication, then the operation can be completed with standard arithmetic procedures, but the computational bottleneck increases and processing time is extended
Solution Approach 1:
The patent pre-stores multiplication tables in the memory device before computation is needed. By having the multiplication factors already stored in the memory cells, the system eliminates the need for real-time computation of multiplication factors during the actual multiplication operation. When a multiplication is required, the system simply retrieves the pre-prepared results by applying voltages to the appropriate memory cells, significantly reducing processing time.
Solution Approach 2:
The patent skips the traditional multi-step arithmetic computation process by directly retrieving pre-stored multiplication results from memory. Instead of performing sequential arithmetic operations (load operands, execute multiplication algorithm, store result), the system rushes through the process by applying voltages to memory cells and directly obtaining the multiplication result from the memory device's output, thereby eliminating intermediate computation steps and reducing processing time.
Data Source
AI summary
A floating-point in-memory multiplication device achieving one-step floating-point multiplication operation is disclosed. The device performs multiplication on a multiplicand and a multiplier and generates a first product. Each of the multiplicand, the multiplier and the first product is a binary floating-point number in IEEE 754 format and contains a sign bit, a q-bit exponent and a (p−1)-bit significand. The device comprises a XOR gate device, a decoder circuit, an adder circuit, a binary in-memory multiplier circuit and an encoder circuit. The XOR gate device receives the sign bits of the multiplicand and the multiplier to generate a sign bit of the first product. The adder circuit adds up the q-bit exponents of the multiplicand and the multiplier to generate a (q+1)-bit temporary exponent. The binary in-memory multiplier circuit performs multiplication on a first and a second p-bit significands to generate a 2p-bit second product.