In-Memory Full Adder Circuit With 9-Transistor Logic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional full adder circuits based on static CMOS require a large number of transistors, leading to slow circuit speed and high power consumption, which is unfriendly to circuit performance and integration.
Innovation Solution
A low-area full adder circuit utilizing nonvolatile in-memory computing field-effect transistors, comprising a sum generating circuit and a carry generating circuit, constructed with nine transistors that improve computing speed and integration density by storing data and performing logical operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional static CMOS full adder is used, then the circuit can perform addition operations, but it requires 28 transistors which leads to large circuit area and slow speed
Solution Approach 1:
The patent combines storage and computation functions into a single transistor structure. The nonvolatile in-memory computing field-effect transistor integrates the storage unit (first gate dielectric layer with polarization states) and computing unit (second gate dielectric layer with controlled polarization), eliminating the need for separate storage and logic circuits. This merging reduces the transistor count from 28 in traditional CMOS to just 9 transistors while improving computing speed through in-place computation.
Solution Approach 2:
The nonvolatile in-memory computing field-effect transistor performs multiple functions: it stores data through polarization states of the gate dielectric layer, performs logical operations by controlling polarization switching, and outputs computation results through drain current. This multi-functional transistor replaces multiple specialized components (storage cells, logic gates, read circuits) required in traditional CMOS architecture, significantly reducing device complexity.
2Area of stationary object
If traditional static CMOS full adder is used, then the circuit can perform logical operations, but it consumes very large circuit area
Solution Approach 1:
The patent merges storage and computation into a single transistor, eliminating the need for separate storage cells and logic gates that occupy large areas in traditional CMOS. The full adder circuit is implemented using only 9 nonvolatile in-memory computing field-effect transistors, dramatically reducing the circuit area compared to the 28 transistors required by traditional static CMOS full adders.
Solution Approach 2:
The patent changes the operating principle from voltage-based logic levels in CMOS to polarization-state-based storage and computation. By utilizing the polarization states of the gate dielectric layer as storage states and controlling polarization switching for computation, the circuit achieves high integration density without sacrificing functionality, thereby reducing the overall circuit area.
3Use of energy by moving object
If data is frequently transferred between computing unit and storage unit, then the system can operate, but it causes serious losses in power consumption
Solution Approach 1:
The patent combines storage and computation within the same transistor structure, eliminating the need for data transfer between separate storage units and computing units. The nonvolatile in-memory computing field-effect transistor performs logical operations directly on stored data through in-place computation, where the storage unit (first gate dielectric layer) and computing unit (second gate dielectric layer) are integrated. This eliminates data movement and the associated power consumption, achieving low-power operation.
4Productivity
If nonvolatile in-memory computing field-effect transistors are used, then computing speed and integration density are improved, but the transistor structure becomes more complex
Solution Approach 1:
The patent segments the gate dielectric layer into two distinct parts: a first gate dielectric layer for nonvolatile storage and a second gate dielectric layer for volatile computation. This segmentation allows independent optimization of storage and computing functions while maintaining a relatively simple overall transistor structure. The segmented design enables high computing speed through fast polarization switching in the second layer while preserving data through polarization states in the first layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces data transmission and circuit area, enhancing computing speed and integration density, thereby improving circuit performance and efficiency.
Implementation Method 1
By adjusting the polarization of the gate dielectric layer of the transistor, nonvolatile storage of data can be realized
Data Source
AI summary
The present application discloses a full adder circuit and a multi-bit full adder. In the full adder circuit, an in-memory computing field-effect transistor stores data and performs logic operation on the data in the transistor and the loaded data according to different input signals; and a low-area full adder circuit is realized with very few transistors through the characteristics and the reading and writing modes of the in-memory computing field-effect transistor. The full adder circuit has a simple structure, which is greatly reduces the area and complexity of the full adder circuit, and saves 19 transistors compared with the traditional CMOS full adder circuits.