In-Memory Logic Gate Array for Faster GEMM Computation
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Solution Overview
Problem
Traditional computer architectures face significant delays due to high read and compute times, particularly in artificial-intelligence neural-network computations, which are exacerbated by the need for efficient performance of parallel general matrix multiplication operations.
Innovation Solution
The integration of logic gates within a memory array, where each logic gate is coupled to pairs of memory cells, allowing for efficient computation by performing logical operations directly on stored data within the memory, thereby reducing read and compute times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data are stored in traditional memory and read before calculation, then data storage capacity is maintained, but read time and compute time cause substantial delays in performing calculations
Solution Approach 1:
The patent merges memory storage cells with logic gate circuits into an integrated structure where each memory cell is associated with logic gates that can perform computations directly on stored data. This combination eliminates the need to read data from memory before processing, as computations occur in-place within the memory array, thereby reducing both read time and compute time simultaneously.
Solution Approach 2:
The patent introduces a new dimensional aspect to memory architecture by adding computational capabilities along the memory array structure. Instead of the traditional separate memory-processor architecture, the logic gates are distributed throughout the memory array, creating a three-dimensional integration of storage and computation that enables parallel processing across multiple memory locations.
2Productivity
If logic gates are integrated within memory array, then compute time is reduced, but device complexity increases
Solution Approach 1:
The integrated memory-logic structure serves multiple functions: it stores data in memory cells and simultaneously performs logical operations through associated logic gates. This multi-functionality allows the same physical structure to act as both memory and processor, increasing computation speed while the shared infrastructure helps manage complexity rather than simply adding to it.
Solution Approach 2:
The memory array performs computations on its own stored data without requiring external processing. The logic gates integrated within the memory structure can directly operate on data held in adjacent memory cells, enabling the memory system to serve its own computational needs and reducing dependency on separate processing units.
3Productivity
If logic gates are coupled to pairs of memory rows, then GEMM operations can be performed efficiently, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by associating specific logic gates with specific pairs of memory rows, where each logic gate is optimized to process data from its designated memory cell pair. This localized arrangement allows for efficient GEMM operations where each logic unit handles a specific computational task, and the regular repeating pattern of this local structure across the array simplifies manufacturing compared to fully custom interconnections.
Data Source
AI summary
A memory includes an array with rows and columns of memory cells. The rows include a first row and a second row, which may be adjacent. The memory also includes a plurality of logic gates in the array. Each logic gate of the plurality of logic gates includes a first input coupled to a respective memory cell in the first row, a second input coupled to a respective memory cell in the second row, and an output. The first and second inputs may be connected to internal nodes within the respective memory cells without intervening transistors. The memory further includes a plurality of sense lines in the array. The output of each logic gate of the plurality of logic gates is coupled to a sense line of the plurality of sense lines.