In-Memory MAC Conversion Using Voltage-Controlled Delay Circuits
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Solution Overview
Problem
Existing neural network processing systems face inefficiencies in miniaturization and commercialization due to excessive computational demands and memory access frequency, particularly in handling repetitive multiply-accumulate (MAC) operations, which are not efficiently processed at low power and high speed by current hardware architectures.
Innovation Solution
An in-memory processing apparatus and method that includes a memory cell array, voltage-controlled delay circuits, and a time-digital converter, where the voltage-controlled delay circuits determine delay times based on sampling voltages to output stop signals, and the time-digital converter performs time-digital conversion, enabling efficient processing of MAC operations without the need for individual analog-to-digital converters in each column.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual analog-to-digital converters are used in each column for neural network processing, then conversion precision is improved, but device complexity and circuit area increase
Solution Approach 1:
The patent merges multiple individual analog-to-digital converters into a single shared time-digital converter that serves all column lines. This is achieved by using voltage-controlled delay circuits that convert analog current sums from multiple columns into time-delayed stop signals, which are then processed by one time-digital converter to produce digital outputs for all columns, thereby reducing circuit area while maintaining conversion capability
Solution Approach 2:
The patent introduces voltage-controlled delay circuits as intermediary components between the memory cell array and the time-digital converter. These delay circuits translate analog current information into time-domain signals that can be processed by a single converter, acting as a mediator that enables shared conversion resources while preserving the information from multiple columns
2Measurement precision
If individual analog-to-digital converters are used in each column, then conversion capability is improved, but power consumption increases
Solution Approach 1:
The patent combines multiple individual converters into one shared time-digital converter, directly reducing the total power consumption associated with having multiple separate conversion circuits. The voltage-controlled delay circuits enable this sharing by providing a mechanism to serialize multiple analog inputs into a single converter's input stream
Solution Approach 2:
The patent replaces traditional analog-to-digital conversion mechanisms with a time-domain approach using voltage-controlled delay circuits. This substitution transforms the conversion process from direct analog-digital transformation to an indirect time-based encoding followed by digital conversion, which consumes less power when shared across multiple columns
3Productivity
If more memory cell groups and column lines are added to increase processing capacity, then productivity is improved, but device complexity and area increase
Solution Approach 1:
The patent makes the time-digital converter a universal resource that serves all column lines through the voltage-controlled delay circuits. This multi-functional approach allows a single converter to handle inputs from multiple memory cell groups and column lines, increasing processing capacity without proportionally increasing converter circuit area
Solution Approach 2:
The patent transitions from spatial multiplication of converters (one per column) to temporal multiplexing using voltage-controlled delay circuits. By adding the time dimension through controllable delay periods, the system can process multiple columns sequentially through a single converter, trading spatial complexity for temporal processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves data transfer speed and reduces power consumption and circuit area by integrating a single highly efficient on-chip time-digital converter system, enhancing the processing of neural network operations while minimizing power usage and circuit size.
Implementation Method 1
memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines
Implementation Method 2
voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums
Implementation Method 3
time-digital converter configured to perform time-digital conversion at the second time points
Data Source
AI summary
An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; a time-digital converter configured to perform time-digital conversion at the second time points; and sampling resistors connected to the column lines, wherein the time-digital converter is configured to reset a counter at the first time point, and output counting values as digital values at the second time points.