In-Memory MAC Processing Using Voltage-Controlled Delay Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing neural network processing systems face inefficiencies in miniaturization and commercialization due to excessive computational demands and memory access frequency, particularly in handling repetitive multiply-accumulate (MAC) operations, which are not efficiently processed at low power and high speed by current hardware architectures.
Innovation Solution
An in-memory processing apparatus and method that includes a memory cell array, voltage-controlled delay circuits, and a time-digital converter, where the voltage-controlled delay circuits determine delay times based on sampling voltages to output stop signals, and the time-digital converter performs time-digital conversion, enabling efficient processing of MAC operations without the need for individual analog-to-digital converters in each column.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual analog-to-digital converters are used in each column for neural network processing, then conversion precision is improved, but device complexity and circuit area increase
Solution Approach 1:
The patent merges multiple individual ADC functions into a single shared ADC resource. The memory cell array processes multiple columns of data simultaneously, and a single ADC is time-multiplexed to convert analog signals from different columns sequentially, thereby reducing the total number of ADC components while maintaining conversion precision for each column.
Solution Approach 2:
The single ADC is designed to serve multiple columns universally through time-multiplexed operation. The ADC can be dynamically allocated to different columns based on processing needs, making one component perform the function of what would traditionally require multiple dedicated converters, thus reducing circuit area while preserving precision.
2Productivity
If traditional hardware architecture is used for MAC operations, then computational capability is improved, but power consumption increases
Solution Approach 1:
The patent replaces traditional mechanical/electronic MAC computation hardware with an in-memory computing approach that leverages the inherent electrical properties of memory cells. By performing computations directly within the memory array using voltage and current interactions, the system eliminates the need for separate computational units, thereby maintaining computational capability while significantly reducing power consumption.
3Speed
If traditional hardware architecture is used for MAC operations, then processing speed is improved, but power consumption increases
Solution Approach 1:
The patent substitutes traditional high-speed computational hardware with in-memory computing that achieves comparable processing speeds through direct voltage and current operations within the memory array. This approach maintains processing speed by performing computations in parallel across multiple memory cells simultaneously while consuming less power than sequential electronic computation.
4Productivity
If memory access frequency is increased to handle complex neural network data, then processing capability is improved, but power consumption increases
Solution Approach 1:
The patent merges the storage and computation functions into a single in-memory processing unit. By performing MAC operations directly within the memory array without frequent data transfers between separate memory and processing units, the system maintains high processing capability while eliminating the power consumption associated with repeated memory access operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves data transfer speed and reduces power consumption and circuit area by integrating a single time-digital converter system, enhancing the efficiency of neural network processing and reducing the need for separate ADCs in each column.
Implementation Method 1
memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines
Implementation Method 2
voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums
Implementation Method 3
time-digital converter configured to perform time-digital conversion at the second time points
Data Source
AI summary
An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; and a time-digital converter configured to perform time-digital conversion at the second time points.