In-Memory MAC Circuit for Signed Matrix-Vector Subtraction
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Solution Overview
Problem
Existing in-memory computation systems face challenges in efficiently performing signed matrix vector multiplication operations due to the need for both positive and negative elaborations, which are not adequately supported.
Innovation Solution
An in-memory computation circuit and method that utilizes a memory array with programmable memory cells to store signed computational weights, employing pulse width modulation for word line signals based on the sign bit of the feature data, and a column processing circuit to calculate the difference between positive and negative elaborations using analog-to-digital conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If in-memory computation systems perform signed matrix vector multiplication using both positive and negative elaborations, then the computation accuracy is improved, but the device complexity and power consumption increase
Solution Approach 1:
The patent segments the signed matrix vector multiplication operation into two separate operations: positive elaboration and negative elaboration. Each elaboration handles specific sign combinations independently, allowing the system to achieve accurate signed computation by combining results from these segmented operations while managing complexity through structured separation of computation paths.
Solution Approach 2:
The patent employs dynamic control mechanisms to selectively activate either positive or negative elaboration based on the sign bits of input data. This dynamic approach allows the system to adapt its computation path in real-time, reducing unnecessary operations and managing device complexity while maintaining computation accuracy through conditional execution.
2Productivity
If data is transferred between memory device and computing device, then the computation can be performed, but the power consumption increases and data transfer bandwidth limitations arise
Solution Approach 1:
The patent merges the storage function and computation function into a single integrated in-memory computation system. By combining memory cells with computation circuitry (including sense amplifiers and control logic) within the same memory device, the system eliminates the need for data transfer between separate memory and computing devices, thereby reducing power consumption and overcoming bandwidth limitations while maintaining high computation performance.
3Adaptability or versatility
If only unsigned data is used in in-memory computation, then the device complexity is reduced, but the adaptability to handle signed feature data is limited
Solution Approach 1:
The patent applies local quality by implementing different computation paths (positive and negative elaborations) tailored to specific sign combinations of input data. Each elaboration is optimized for its specific sign scenario, allowing the system to handle signed data with appropriate local computation strategies while maintaining overall system manageability through this localized approach to signed data handling.
Data Source
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AI summary
An in-memory computation circuit includes a memory array with memory cells arranged in a matrix in rows and columns. Groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration to produce a first analog signal and a second MAC elaboration to produce a second analog signal. An analog-to-digital converter circuit operates to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit to a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.