In-Memory MAC Circuit With Built-In Subtraction for Signed MVM
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Solution Overview
Problem
Existing in-memory computation systems face challenges in efficiently performing signed multiply and accumulate operations due to the need for both positive and negative elaborations, which are not adequately addressed in current technologies.
Innovation Solution
An in-memory computation circuit with a memory array and analog-to-digital converter circuit that performs first and second multiply and accumulate elaborations, incrementing a count value and converting it to a negated count value using a 2's complement operation, to handle signed feature and weight data efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If signed MAC operations are performed with both positive and negative elaborations, then computation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the positive and negative elaboration results within a single memory array by using complementary bit line pairs (BL<A>+ and BL<A>-). The ADC circuit combines both elaborations sequentially, performing the 2's complement operation on the negative elaboration result and adding it to the positive elaboration result, thereby achieving accurate signed MAC operations without requiring separate memory arrays for each elaboration type.
Solution Approach 2:
The patent employs periodic action by sequentially performing the positive elaboration first, then the negative elaboration, with each elaboration completing before the next begins. This sequential periodic execution allows the system to handle both positive and negative weight contributions systematically, ensuring computation accuracy while managing device complexity through time-multiplexed operation.
2Adaptability or versatility
If data is transferred between memory device and computing device, then computation flexibility is improved, but power consumption increases
Solution Approach 1:
The patent implements self-service by enabling the memory array to perform MAC operations directly at the storage location. The memory cells themselves conduct the multiplication and accumulation operations using their stored weight values, eliminating the need to transfer data between separate memory and computing devices. This in-memory computation approach maintains computation flexibility while dramatically reducing power consumption associated with data movement.
3Adaptability or versatility
If data is transferred between memory device and computing device, then computation flexibility is improved, but data transfer bandwidth requirements increase
Solution Approach 1:
The memory array performs MAC operations in-place, with each memory cell contributing its stored weight value directly to the computation without requiring data extraction and re-input. The analog computation results are converted to digital values and stored back in the same memory structure, eliminating the need for high-bandwidth data transfer interfaces between separate memory and computing devices.
Solution Approach 2:
The patent introduces an analog-to-digital converter (ADC) circuit as an intermediary between the analog memory array and the digital processing domain. This ADC performs the critical function of converting analog computation results to digital values, enabling the system to maintain computation flexibility while avoiding the need for high-bandwidth digital data transfer interfaces.
Data Source
AI summary
An in-memory computation circuit includes a memory array with memory cells arranged in a matrix in rows and columns. Groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration to produce a first analog signal and a second MAC elaboration to produce a second analog signal. An analog-to-digital converter circuit operates to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit to a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.