In-Memory Arithmetic Unit Layout for Pipelined Multi-Bank Access
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Solution Overview
Problem
Existing memory devices face challenges in efficiently performing arithmetic operations due to the addition of separate processing hardware, requiring methods to enhance arithmetic operation processing efficiency.
Innovation Solution
A memory device configured with in-memory arithmetic units and memory banks, where each unit operates at a frequency less than or equal to the product of the number of memory banks it accesses, allowing pipelined arithmetic operations with multiplexers and bank selectors to optimize data access and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate processing hardware is added to a memory device to enable in-memory processing, then arithmetic operation capability is improved, but device complexity increases
Solution Approach 1:
The patent combines memory storage functions with arithmetic processing functions into a single integrated device. Memory banks are directly coupled with arithmetic logic units, allowing data to be processed in-place without external processing hardware. This merging approach enables in-memory processing while avoiding the complexity of separate processing units and their interconnections.
Solution Approach 2:
The memory device is designed to perform multiple functions: it can store data in memory banks and simultaneously perform arithmetic operations on that data. The arithmetic logic units can execute various computational tasks including multiplication, accumulation, and logical operations, making the memory device a multi-functional component that reduces overall system complexity.
2Productivity
If in-memory arithmetic units are added to perform computational operations, then processing efficiency is improved, but the burden of arithmetic operations on the computing system is not sufficiently reduced
Solution Approach 1:
The memory device is divided into multiple independent memory banks, each capable of being accessed by dedicated arithmetic logic units. This segmentation allows parallel processing of multiple data sets simultaneously, significantly improving processing efficiency and reducing the computational burden on external systems through distributed in-memory computation.
Solution Approach 2:
The patent implements pipelined arithmetic operations where data flows continuously through multiple processing stages. While one operation is being executed, the next data set is being prepared, ensuring continuous utilization of arithmetic resources. This eliminates idle time and maximizes processing throughput, thereby reducing overall computational burden.
3Speed
If memory banks are allocated to in-memory arithmetic units for simultaneous access, then data access speed is improved, but frequency matching between arithmetic units and memory banks becomes complex
Solution Approach 1:
The patent employs dynamic frequency adjustment mechanisms where the operating frequency of arithmetic logic units is adaptively matched to the speed of memory banks. This dynamic synchronization allows the system to optimize data access speed while automatically handling frequency coordination, preventing the need for complex static frequency matching circuits.
Solution Approach 2:
Control logic acts as an intermediary between memory banks and arithmetic logic units, managing data transfer and frequency coordination. This intermediary component simplifies the interface by handling frequency matching and data routing automatically, allowing both memory banks and arithmetic units to operate at their optimal speeds without direct complex interactions.
Data Source
AI summary
A memory device configured to perform in-memory processing includes a plurality of in-memory arithmetic units each configured to perform in-memory processing of a pipelined arithmetic operation, and a plurality of memory banks allocated to the in-memory arithmetic units such that a set of n memory banks is allocated to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested from the in-memory arithmetic units while the pipelined arithmetic operation is performed. Each of the in-memory arithmetic units is configured to operate at a first operating frequency that is less than or equal to a product of n and a second operating frequency of each of the memory banks.