In-Memory Device Multi-Bit Weight Hierarchical Summation
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Solution Overview
Problem
Existing in-memory devices require an exponentially increasing number of capacitors and chip area to support multi-bit weights, making it impractical to implement hardware for tasks like super-resolution restoration that require high bit-width operations, as they can only support binary weights, leading to performance degradation and area overhead.
Innovation Solution
A hierarchical summation method is introduced in the in-memory device, utilizing a multi-bit memory cell array with a DAC to convert digital signals to analog voltages, performing multiplication and summation with multi-bit weights, and an ADC to convert the final output back to digital, reducing the number of capacitors needed by dividing bit weights into groups and sharing charges across capacitors with varying capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional capacitors are added to expand array columns to apply multi-bit weight, then the bit-width of weight is increased, but the chip area and number of capacitors increase exponentially
Solution Approach 1:
The patent segments the weight bit-width into multiple groups, where each group is processed by a separate capacitor. Instead of using one capacitor per bit (which would require 8 capacitors for 8-bit weight), the patent groups bits together (e.g., 2 bits per group), requiring only 4 capacitors for 8-bit weight. This segmentation reduces the exponential growth of capacitors while maintaining the precision of multi-bit weight operations.
2Measurement precision
If additional capacitors are added to expand array columns to apply multi-bit weight, then the bit-width of weight is increased, but the number of capacitors increases by a power of 2
Solution Approach 1:
The patent segments the weight bit-width into multiple groups, where each group is processed by a separate capacitor. Instead of using one capacitor per bit (which would require 8 capacitors for 8-bit weight), the patent groups bits together (e.g., 2 bits per group), requiring only 4 capacitors for 8-bit weight. This segmentation reduces the exponential growth of capacitors while maintaining the precision of multi-bit weight operations.
3Device complexity
If binary weight is used in in-memory device, then the device complexity is reduced, but the performance for tasks like super-resolution restoration degrades
Solution Approach 1:
The patent introduces dynamic control signals (first control signal and second control signal) that enable the memory device to switch between different weight operation modes. The control logic dynamically selects whether to perform binary weight operations or multi-bit weight operations based on the input data characteristics, allowing the device to adapt its complexity level to match the performance requirements of different tasks.
Solution Approach 2:
The patent changes the parameter of weight bit-width from fixed binary (1-bit) to variable multi-bit configuration. By allowing the weight bit-width to be adjusted based on task requirements, the system can maintain high performance for tasks like super-resolution restoration that require multi-bit precision, while still supporting simpler binary operations when appropriate, thus balancing complexity and performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the number of capacitors and chip area required for multi-bit weight operations, achieving efficient summation and maintaining performance while minimizing additional capacitor usage, with a reduction of approximately 88% in capacitors and 95% when dividing 8-bit weights into four two-bit groups.
Implementation Method 1
a DAC which converts a digital input signal into an analog input voltage
Implementation Method 2
performing multiplication and summation with multi-bit weights, and an ADC to convert the final output back to digital, reducing the number of capacitors needed by dividing bit weights into groups and sharing charges across capacitors with varying capacitances
Implementation Method 3
an ADC to convert the final output back to digital
Data Source
AI summary
Disclosed is an in-memory device for operation of a multi-bit weight. A multi-bit memory cell array according to an exemplary embodiment of the present invention includes at least one multi-bit unit which stores input data based on an input signal and outputs a per-group sum value summed for every group by applying a multi-bit weight to the stored input data; and a final summation unit which is connected to at least one multi-bit unit, adjusts a ratio for every group to receive the peer-group sum value, and outputs a final output value by summing the input per-group sum value.