In-Memory Multiplier Devices for Binary Multiplication
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Solution Overview
Problem
In Von Neumann computing architecture, binary multiplication processes are inefficient due to high power consumption and bus-line congestions caused by frequent bit-level manipulations and data transportation, leading to slowed computation and increased silicon area requirements as the number of processing bits increases.
Innovation Solution
Implementing multiple-digit binary in-memory multiplication devices that utilize memory arrays to store base-2n multiplication tables, reducing operational steps and data transportation by representing numbers in base-2n format, and using Perpetual Digital Perceptron (PDP) units with CROM and RROM arrays for direct arithmetic computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional binary multiplication with bit-level manipulations is used, then multiplication can be performed, but power consumption increases significantly and computation speed decreases
Solution Approach 1:
The patent segments the binary multiplication process into multiple-digit base-2n operations. Instead of processing one bit at a time, the system divides the n-bit binary codes into multiple-digit groups (e.g., 2n-bit groups), reducing the total number of operational steps from O(n^2) to O(n), thereby improving computation speed and reducing power consumption.
Solution Approach 2:
The patent replaces the conventional mechanical bit-level manipulation system with an in-memory computation system. Memory arrays store base-2n multiplication tables, allowing direct lookup and multiplication of multiple-digit groups without sequential bit-level operations, significantly reducing the computational overhead and power consumption associated with moving data through multiple memory units and logic gates.
2Productivity
If more operational steps are used for bit-level manipulations, then multiplication accuracy is maintained, but bus-line congestion increases and computation is slowed
Solution Approach 1:
The patent segments data transportation into larger base-2n digit groups rather than individual bits. This reduces the number of data transportation operations from O(n^2) to O(n), decreasing bus-line congestion and improving computation speed while maintaining multiplication accuracy through the use of stored base-2n multiplication tables.
3Area of stationary object
If conventional binary multiplication methods are used, then standard binary operations are performed, but silicon area increases with the number of processing bits
Solution Approach 1:
The patent segments the multiplication process into multiple-digit base-2n operations, reducing the number of required logic gates and memory units. By processing multiple bits simultaneously in each operational step, the system achieves higher processing capability with reduced silicon area compared to conventional bit-level multiplication methods.
Solution Approach 2:
The patent transitions from one-dimensional bit-level processing to multi-dimensional base-2n digit processing. By organizing binary codes into multiple-digit groups and using memory arrays to store base-2n multiplication tables, the system efficiently utilizes silicon area to achieve higher processing capability without linearly increasing the number of processing bits.
Data Source
AI summary
The multi-digit binary in-memory multiplication devices are disclosed. The multi-digit binary in-memory multiplication devices of the invention can dramatically reduce the operational steps in comparison with the conventional binary multiplier device. In one embodiment with the expense of more hardware, the in-memory multiplication device can achieve one single step operation. Consequently, the multi-digit binary in-memory multiplication device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU), registers, and memory units.