In-Memory Computing Multiplying Cell for Neural Network Processing
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Solution Overview
Problem
Existing memory devices with in-memory computing (IMC) face challenges in efficiently performing vector-matrix multiplication operations, which are central to neural network processing, due to limitations in performance and power efficiency.
Innovation Solution
A memory device with a multiplying cell structure that includes a memory cell with a pair of inverters and transistors, along with a switching element acting as a pull-up transistor, which selects between two operations to optimize voltage driving and pre-charge phases for efficient multiplication and accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional memory cell structure is used for in-memory computing, then the device complexity is reduced, but the performance and power efficiency of vector-matrix multiplication operations deteriorate
Solution Approach 1:
The patent merges the memory cell with additional transistors (first and second transistors connected to the pair of inverters) and a switching element to create an integrated multiplying cell. This combination enables the cell to perform both storage and multiplication operations, improving productivity through in-memory computing while managing device complexity through functional integration.
Solution Approach 2:
The multiplying cell structure is designed to perform multiple functions: storing data in the memory cell, performing multiplication operations through the transistors and switching element, and selectively operating in different modes (first operation for some multiplication operations, second operation for pre-charge and evaluation phases). This multi-functionality improves computing performance without requiring separate dedicated circuits.
2Use of energy by moving object
If a single operation mode is used in the memory device, then the device complexity is reduced, but the power efficiency and performance optimization deteriorate
Solution Approach 1:
The patent implements a dynamic operation selection mechanism where the switching element can selectively perform either the first operation (driving voltage to supply voltage in response to voltage less than supply voltage applied through word line) or the second operation (driving voltage to supply voltage in pre-charge phase and performing multiplication in evaluation phase). This dynamic adaptability optimizes power efficiency for different operational scenarios while managing complexity through conditional logic.
3Speed
If voltage is continuously driven to supply voltage, then the multiplication operation speed is improved, but the power consumption increases
Solution Approach 1:
The patent implements periodic voltage driving through the second operation mode, where the switching element drives voltage to supply voltage during pre-charge phases and performs multiplication operations during evaluation phases in an alternating sequence. This periodic action maintains multiplication speed by ensuring proper voltage levels are established while reducing power consumption by only driving voltage when necessary during pre-charge phases rather than continuously.
Data Source
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AI summary
A memory device performs a multiplication operation using a multiplying cell including a memory cell and a switching element, in which the memory cell includes a pair of inverters connected to each other in opposite directions, a first transistor connected to one end of the pair of inverters, and a second transistor connected to the other end of the pair of inverters, and has a set weight; and the switching element is connected to an output end of the memory cell and configured to perform switching in response to an input value and output a signal corresponding to a multiplication result between the input value and the weight.