In-Memory Programmable Logic for Data Packet Switching

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Solution Overview

Problem

Traditional computing systems require significant CPU/GPU resources and I/O bandwidth for processing and switching data packets, leading to bottlenecks in high-traffic networks, as they rely on software to perform even minor logic tasks, which can hinder performance in virtual and logical switching environments.

Innovation Solution

Implementing programmable logic within hardware components such as memory and network interface controllers (NICs) to process and manipulate data packets directly, reducing the need for CPU/GPU involvement and conserving I/O bandwidth through in-memory acceleration logic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If software is used to process data packets in traditional computing systems, then the system can handle basic networking tasks, but CPU/GPU resources and I/O bandwidth are significantly consumed leading to performance bottlenecks in high-traffic networks

Engineering Contradiction:

Improvedata packet processing throughputVSAvoidCPU/GPU resource consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent replaces software-based packet processing (mechanical system) with hardware-based processing using network interface controllers and smart NICs that can perform packet switching, filtering, and forwarding operations directly in hardware, eliminating the need for CPU/GPU intervention in routine networking tasks

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces an intermediary layer (smart NIC with buffer memory and logic circuits) between the network and the CPU/GPU that handles packet processing operations, allowing the main processor to focus on computationally intensive tasks while the intermediary handles routine networking operations

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of operation

If software processes every data packet through the operating system, then packet handling is straightforward, but I/O bandwidth is consumed and performance is hindered in high-traffic scenarios

Engineering Contradiction:

Improvepacket handling simplicityVSAvoidI/O bandwidth consumption

Core Design Contradiction:

Ease of operationVSLoss of energy

Solution Approach 1:

The patent segments packet processing operations into two paths: simple packets are handled directly by the smart NIC hardware without OS involvement, while complex packets requiring special processing are forwarded to the OS, thereby reducing overall I/O bandwidth consumption

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary packet processing actions (filtering, forwarding decisions, basic modifications) in the smart NIC buffer memory before packets reach the OS, so that many packets are handled and discarded or forwarded without consuming OS I/O bandwidth

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentEP4020933A1Methods and apparatus to process data packets for logical and virtual switch acceleration in memory

Publication Date: 2022.06.29 INTEL CORP

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AI summary

Methods, apparatus, systems, and articles of manufacture to process data packets for logical and virtual switch acceleration in memory are disclosed. An example memory includes an input packet buffer to store an inbound data packet from a network; an output packet buffer to store an outbound data packet to transmitted via the network; and programmable logic to: read the inbound data packet from the input packet buffer; process the inbound data packet to determine the outbound data packet; and output the outbound data packet to the output packet buffer.