In-Memory Processing Subarrays for Data Movement Bottlenecks

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Solution Overview

Problem

Current memory devices face inefficiencies in data processing due to repeated movements of data values between storage and cache memory cells, leading to reduced speed and increased power consumption during sequential operations.

Innovation Solution

Implementing a memory device with a PIM structure that includes subarrays with shorter and longer digit lines, where the subarrays with shorter digit lines serve as caches for faster data processing and those with longer digit lines are used for data storage, along with a controller that directs data movements and operations to optimize performance and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is repeatedly moved between storage and cache memory cells for sequential operations, then data processing can be completed, but processing speed decreases and power consumption increases

Engineering Contradiction:
Improvedata processing speedVSAvoidtime for data movement
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The memory array is divided into multiple partitions, with each partition containing both storage subarrays and cache subarrays. This segmentation allows data to be processed locally within partitions without requiring repeated movements to external cache memory, thereby improving processing speed and reducing time loss.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a spatial dimension by organizing memory into a two-dimensional structure with storage subarrays and cache subarrays within each partition. This allows simultaneous access to both storage and cache functions within the same memory device, eliminating the need for sequential data movement between separate memory components.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If data is repeatedly moved between storage and cache memory cells, then operations can be performed, but power consumption increases

Engineering Contradiction:
Improveoperation throughputVSAvoidpower consumption for data transfer
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

By segmenting the memory into partitions with integrated storage and cache subarrays, the patent enables local data processing that minimizes data transfer distances. This reduces the energy required for data movement while maintaining high operation throughput.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each partition is self-sufficient, containing both storage and cache functionality. This allows data to be cached and processed locally without requiring external memory controllers or additional data movement, reducing power consumption while maintaining productivity.

Inventive Principle:
Principle #25Self-service

3Speed

If subarrays with shorter digit lines are used for caching, then data processing speed increases, but device complexity increases

Engineering Contradiction:
Improvedata access speedVSAvoidmemory structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The memory is segmented into partitions with distinct storage and cache subarrays. This segmentation allows optimization of digit line lengths for different functions (shorter for cache, longer for storage) without requiring a completely complex new architecture, as the segmentation follows existing memory organization principles.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The same memory cell structure is used for both storage and cache subarrays, with the difference being in the digit line connectivity. This multi-functionality approach allows the system to achieve different performance characteristics (speed for cache, capacity for storage) using a unified design, reducing overall complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10915249B2Apparatuses and methods for in-memory operations
Publication Date: 2021.02.09 MICRON TECHNOLOGY INC
  • US10915249B2 patent drawing
  • US10915249B2 patent drawing
  • US10915249B2 patent drawing

AI summary

The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The apparatus also includes a controller configured to direct a first movement of a number of data values from a subarray in the second subset to a subarray in the first subset and performance of a sequential plurality of operations in-memory on the number of data values by the first sensing circuitry coupled to the first subset.