In-Memory Processor Charge Sharing for Parallel Boolean Logic
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Solution Overview
Problem
The bottleneck in computing devices is the bus connection, which has not kept pace with the increased speed of central processing units, limiting the overall operation speed due to slower bus speeds compared to CPU advancements.
Innovation Solution
A NOR device and in-memory processor are developed, utilizing a memory array with multiple memory cells, each comprising a storage capacitor and transistor connected to a read line, allowing simultaneous activation of cells to generate Boolean functions without the need for a bus, using a multiple row decoder and output unit to perform operations like NOR, OR, AND, and NAND gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CPU speed is increased, then processing capability is improved, but bus connection speed becomes a bottleneck limiting overall operation speed
Solution Approach 1:
The patent merges the memory array and processing unit into a single integrated structure where processing operations are performed directly within the memory array. This eliminates the need for separate bus connections between CPU and memory, allowing processing to occur in-place and removing the bus speed bottleneck that limited overall operation speed when CPU speed was increased.
Solution Approach 2:
The patent introduces sense amplifiers as intermediary components that enable direct reading and processing of multiple memory cells simultaneously. These sense amplifiers act as mediators between the memory cells and output, allowing parallel processing operations without requiring high-speed bus connections, thus resolving the bottleneck issue.
2Quantity of substance
If memory array size is increased to store more data, then storage capacity is improved, but physical area occupied increases
Solution Approach 1:
The patent makes the memory array multi-functional by enabling it to perform both storage and processing operations. The same memory cells that store data are also used for processing operations through selective activation of rows and columns. This eliminates the need for separate processing circuits, reducing overall chip area while maintaining large storage capacity.
Solution Approach 2:
The patent exploits the two-dimensional structure of the memory array (rows and columns) to enable parallel processing. By activating multiple rows and columns simultaneously, the system can process multiple data elements in parallel within the same physical area, effectively increasing computational capacity without proportionally increasing physical footprint.
3Productivity
If multiple rows are activated simultaneously for parallel processing, then processing speed is improved, but charge sharing between cells causes read errors
Solution Approach 1:
The patent applies preliminary actions by pre-charging sense amplifier nodes to a known voltage state before reading memory cells. This pre-charging compensates for the charge sharing effect that occurs when multiple cells are read simultaneously, ensuring that the final voltage level accurately reflects the logical OR result rather than being corrupted by charge distribution effects.
Solution Approach 2:
The patent converts the harmful charge sharing effect into a beneficial feature by designing the read operation to exploit capacitive coupling. When multiple memory cells are read simultaneously, the charge sharing between cells through the bit line is used to implement a logical OR function directly in the analog domain, eliminating the need for additional logic circuits and enabling parallel processing without requiring extra area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables faster computing operations within the memory array, eliminating the need for a bus to transfer data, allowing for massively parallel processing and reducing real estate on a chip, while implementing any Boolean operation on multiple columns simultaneously.
Implementation Method 1
each of the memory cells include at least a storage capacitor
Data Source
AI summary
A memory cell includes a storage capacitor, a read line, and a storage transistor, where the storage transistor is connected to the read line and is subject to activation by a charge in the storage capacitor. An in-memory processor includes a memory array which stores data, and an activation unit to activate at least two cells in a column of the memory array at generally the same time, thereby to generate a Boolean function output of the data of the at least two cells, wherein each of the at least two cells includes at least a storage capacitor, a storage transistor and a read line, where the storage transistor is connected to the read line and subject to activation by a charge in the storage capacitor.