In-Memory Semiconductor Read Circuit for Low-Power Data Processing
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Solution Overview
Problem
The classical Von Neumann computing architecture is bottlenecked by high power consumption and limited processing speed due to frequent data migration between memory and processor, exacerbated by massive data processing in applications like big data and artificial intelligence.
Innovation Solution
A semiconductor device with a memory array and peripheral circuit that applies specific voltages to word lines and select lines to sense currents on bit lines, enabling simultaneous input of input voltages for memory cell strings and facilitating complex operations, thereby improving operation flexibility and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transmitted between memory and processor through a data bus in Von Neumann architecture, then data access is enabled, but power consumption increases and processing speed is limited
Solution Approach 1:
The patent merges the memory array with peripheral circuits including sense amplifiers, voltage generation circuits, and control logic into a single integrated semiconductor device. This integration eliminates the need for separate data transmission between independent memory and processor components, thereby reducing power consumption and improving processing speed by enabling in-memory computation operations.
2Productivity
If frequent data migration occurs between memory and processor, then data processing is completed, but time overhead increases
Solution Approach 1:
The patent implements preliminary action by pre-charging sensing nodes and pre-positioning voltage levels in the peripheral circuits before actual read operations. The sense amplifiers are prepared in advance, and voltage generation circuits are configured to provide required voltages immediately, reducing the time overhead associated with data migration and enabling faster data processing throughput.
3Speed
If memory bandwidth is limited, then memory structure is simplified, but processor access speed is constrained
Solution Approach 1:
The patent transitions from traditional planar memory architecture to a three-dimensional stacked memory structure with multiple memory blocks arranged vertically. This dimensional change increases memory bandwidth capacity without proportionally increasing device footprint, allowing faster processor access speeds while managing device complexity through vertical integration.
4Adaptability or versatility
If multiple voltages are applied to word lines and select lines for complex operations, then operation flexibility is improved, but circuit complexity increases
Solution Approach 1:
The patent implements multi-functionality by designing the peripheral circuit to generate multiple different voltages (first voltage, second voltage, third voltage) using a unified voltage generation circuit. This circuit can selectively output different voltage levels to different word lines and select lines based on operation requirements, providing high operation flexibility while avoiding the need for separate dedicated voltage generation circuits for each function, thus controlling device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces data transmission and power consumption, enhancing computing performance by embedding computing functions in memory, allowing for high-bandwidth and energy-efficient operations.
Implementation Method 1
a threshold voltage of the memory cell having the first memory state is less than a threshold voltage of the memory cell having the second memory state
Implementation Method 2
sense a current on a bit line coupled to the target memory block
Data Source
AI summary
Semiconductor devices, methods of operating thereof, systems and computer readable storage mediums are provided. An example semiconductor device includes a memory array and a peripheral circuit coupled to the memory array. The memory array includes a plurality of memory blocks. During an operation phase using the semiconductor device, the peripheral circuit is configured to: apply a first read voltage to a target word line coupled to a target memory block, apply a corresponding input voltage to a plurality of first select lines coupled to the target memory block respectively, apply a first turn-on voltage to a non-target word line coupled to the target memory block, and sense a current on a bit line coupled to the target memory block.