In-Memory Spiking Neural Network Architecture for I/O Bottleneck Resolution
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Solution Overview
Problem
Conventional computer simulations of spiking neural networks (SNNs) face inefficiencies due to the need for separate processing and memory chips, leading to significant input/output traffic that limits their feasibility and performance.
Innovation Solution
An in-memory neural network architecture that integrates a memory structure with a sense amplifier and on-chip processor to store and update post-synaptic information directly within the memory array, bypassing off-chip communications and optimizing learning performance by leveraging DRAM for parallel processing and synaptic weight updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate processing and memory chips are used to support large scale SNNs, then the computational capability is improved, but the input/output traffic between chips increases significantly
Solution Approach 1:
The patent merges processing and memory functions into a single integrated chip architecture. The memory array is directly accessed by processing elements through row activation, eliminating the need for separate processing and memory chips. This integration significantly reduces input/output traffic between chips while maintaining computational capability for large-scale SNNs.
2Productivity
If multi-chip arrays of SRAM are used to support large scale SNNs, then the computational capability is improved, but the device complexity increases
Solution Approach 1:
The patent combines memory storage and processing functions into a single chip, eliminating the need for multi-chip SRAM arrays. The memory array directly stores neural network data and is accessed by processing elements through row activation, reducing device complexity while maintaining computational capability.
Solution Approach 2:
The memory array serves multiple functions: it stores neural network data, provides row activation for parallel processing, and enables direct access by processing elements. This multi-functionality reduces the need for separate dedicated components, simplifying the overall device architecture.
3Speed
If conventional SRAM architecture is used, then the processing speed is maintained, but the memory density is limited
Solution Approach 1:
The patent changes the memory architecture from conventional SRAM to a row-activated memory structure that enables parallel processing. This parameter change allows the system to achieve both high processing speed through parallel row activation and high memory density by eliminating the need for multiple SRAM chips.
Data Source
AI summary
Systems, apparatuses and methods may provide for a chip that includes a memory array having a plurality of rows corresponding to neurons in a spiking neural network (SNN) and a row decoder coupled to the memory array, wherein the row decoder activates a row in the memory array in response to a pre-synaptic spike in a neuron associated with the row. Additionally, the chip may include a sense amplifier coupled to the memory array, wherein the sense amplifier determines post-synaptic information corresponding to the activated row. In one example, the chip includes a processor to determine a state of a plurality of neurons in the SNN based at least in part on the post-synaptic information and conduct a memory array update, via the sense amplifier, of one or more synaptic weights in the memory array based on the state of the plurality of neurons.