In-Memory TLB Augmentation for MMU Translation Efficiency
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Solution Overview
Problem
The existing memory management unit (MMU) in processor-based systems faces inefficiencies in translating virtual addresses (VAs) to physical addresses (PAs) due to frequent page table walks and TLB thrashing, especially in virtual environments where guest virtual machines require translations through multiple page tables, leading to increased translation overhead.
Innovation Solution
The implementation of dedicated in-memory translation lookaside buffers (TLBs) that cache page table entries in system memory, allowing for faster VA to PA translations by reducing the need for full page table walks and enabling per-process TLBs with varying sizes based on memory access patterns, thus avoiding TLB thrashing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the MMU TLB size is increased to reduce translation overhead, then translation efficiency is improved, but device complexity and cost increase
Solution Approach 1:
The patent introduces a new dimension to the TLB hierarchy by placing additional TLB structures in system memory rather than confining all TLBs to the MMU. This creates a two-level TLB system where the first level is the traditional MMU TLB and the second level is the memory-resident TLB, allowing the system to scale translation capacity without proportionally increasing MMU complexity
Solution Approach 2:
The patent introduces an intermediary structure (memory-resident TLB) between the MMU TLB and the page tables. This intermediary caches page table entries in system memory, reducing the frequency of page table walks and the need to access the full page table hierarchy, thereby improving translation efficiency without requiring a larger MMU TLB
2Reliability
If per-process TLBs are implemented to avoid TLB thrashing, then translation stability is improved, but device complexity increases
Solution Approach 1:
The patent segments the TLB into process-specific instances that are isolated in system memory. Each process has its own TLB structure located in memory, which prevents TLB thrashing by ensuring that page table entries for different processes are cached separately. This segmentation improves translation stability while the complexity is managed through software-based process identification and TLB allocation mechanisms
3Productivity
If dedicated in-memory TLBs are added to cache page table entries, then memory access performance is improved, but loss of time for TLB management operations increases
Solution Approach 1:
The patent implements preliminary action by pre-caching page table entries in the memory-resident TLB before they are needed for translation. When a process is loaded or when page tables are modified, the relevant entries are proactively cached in the memory-resident TLB, so that when translation requests arrive, the information is already available, reducing translation time and managing TLB management overhead efficiently
Data Source
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AI summary
Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting a memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PA) in a processor-based system is disclosed. In disclosed examples, a dedicated in-memory TLB is supported in system memory for each process so that one process's cached page table entries do not displace another process's cached page table entries. When a process is scheduled to execute in a central processing unit (CPU), the in-memory TLB address stored for such process can be used by page table walker circuit in the CPU MMU to access the dedicated in-memory TLB for executing the process to perform VA to PA translations in the event of a TLB miss to the MMU TLB. If a TLB miss occurs to the in-memory TLB, the page table walker circuit can walk the page table in the MMU.