In-Memory Trace Capture with Memory Data Contents
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Solution Overview
Problem
Current in-memory trace (IMT) data capture methods in data processing systems do not include memory data contents, which limits the generation of CAP test cases and performance verification for new processor cores, particularly for reflecting new customer workloads and new instruction sets.
Innovation Solution
The method involves initiating an in-memory trace data capture for a processor, capturing the contents of architected registers, and using a load-store unit to read memory data contents, including memory fetch control and data records, to generate and verify hardware instruction traces with memory data contents, enabling the creation of CAP test cases and performance verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If in-memory trace data capture is performed without memory data contents, then the tracing system can operate with simpler infrastructure, but it cannot generate CAP test cases or perform comprehensive performance verification for new processor cores
Solution Approach 1:
The patent combines traditional tracing infrastructure with memory data content capture by integrating the trace data path with memory data paths. The trace unit is enhanced to capture both instruction traces and associated memory data contents, merging these previously separate functions into a unified tracing system that provides comprehensive data for CAP test case generation and performance verification
2Adaptability or versatility
If memory data contents are included in IMT trace data, then CAP test cases can be generated and performance verification can be performed, but the complexity of the trace data capture system increases
Solution Approach 1:
The trace unit is designed with multi-functionality to handle both traditional instruction tracing and memory data content capture. The same trace unit infrastructure processes both types of data, and the trace data format is structured to accommodate multiple data types (instruction traces, memory data contents, and their associations) within a unified framework, reducing the need for separate dedicated hardware for each function
3Measurement precision
If memory data contents are captured in IMT traces, then comprehensive performance verification is enabled, but the amount of data to be processed and stored increases
Solution Approach 1:
The trace data is segmented into distinct components including instruction traces, memory data contents, and association information. This segmentation allows for organized storage and selective processing of different data types, enabling the system to handle comprehensive verification data while managing data volume through structured organization and efficient storage of only relevant portions
Data Source
AI summary
Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.