In-Memory Zero Value Detection Integrated Circuit Architecture
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Solution Overview
Problem
Current computer architectures face limitations due to the von Neumann bottleneck, which restricts processing speed due to throughput limitations in data transfer between memory and processors, especially in memory-intensive tasks like neural networks and database operations.
Innovation Solution
The proposed solution involves an integrated circuit with a substrate hosting a memory array with discrete memory banks and a processing array with processor subunits, each associated with dedicated memory banks. This architecture includes a controller for implementing security measures and remedial actions, and it allows for partial or no refreshes on memory chips, enabling selectable-sized memory chips and dual-port capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data transfer between memory and processor is increased to meet computational bandwidth requirements, then processing speed improves, but throughput limitations of conventional architecture cause clock cycle consumption to increase
Solution Approach 1:
The patent combines memory and processing functions into a single integrated circuit substrate, eliminating the von Neumann bottleneck by allowing processors to access memory without traditional bus limitations. This merging enables simultaneous data access and computation, improving processing speed without proportionally increasing clock cycle consumption.
Solution Approach 2:
The integrated circuit divides the processing function into multiple processor subunits, each capable of independent operation. This segmentation allows parallel processing of data, increasing overall processing speed while distributing clock cycle consumption across multiple units, thereby improving efficiency.
2Quantity of substance
If memory size is increased to handle larger data sets, then data processing capability improves, but memory access latency increases
Solution Approach 1:
The memory is divided into multiple discrete memory banks that can be accessed independently and simultaneously. This segmentation allows the system to handle large data sets across multiple banks while maintaining low latency by accessing different banks in parallel, rather than sequentially accessing a single large memory block.
Solution Approach 2:
The patent introduces a spatial dimension to memory access by organizing data across multiple parallel memory banks. Instead of accessing a single large memory block sequentially, the system can access multiple smaller banks simultaneously in parallel, effectively adding a temporal dimension to memory access and reducing overall latency.
3Productivity
If parallel processing is implemented to handle massive data, then data processing capability improves, but resource requirements for data management increase
Solution Approach 1:
The patent merges memory and processing resources into a unified integrated circuit, eliminating the need for separate data management infrastructure. This consolidation enables parallel processing while reducing overall resource requirements, as the shared architecture allows multiple processor subunits to access memory directly without additional management overhead.
4Ease of manufacture
If fabrication techniques for common chips are used for data-intensive chips, then manufacturing ease is maintained, but performance and yield become poor
Solution Approach 1:
The patent employs fabrication parameters optimized for memory operations rather than arithmetic computation. By changing the fabrication parameters to suit memory-intensive workloads, the system achieves both high performance and good yield while maintaining reasonable manufacturing complexity through the use of established semiconductor fabrication processes.
Data Source
AI summary
In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.