In-Mold Capacitor Embedded in Molding Compound for IC Package

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Solution Overview

Problem

Conventional decoupling capacitors have a large footprint, posing challenges for ultra-small form factor packaging technologies in integrated circuit (IC) packaging, particularly in reducing the package form factor and improving routing density.

Innovation Solution

The development of an over-molded IC package with embedded in-mold capacitors, where conductive plates are embedded within a molding compound and separated by a high-permittivity dielectric material, reducing the footprint and allowing capacitors to be placed in trenches or vias, enabling a more compact design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional decoupling capacitors are used, then decoupling performance is achieved, but package footprint becomes too large for ultra-small form factor packaging

Engineering Contradiction:
Improvedecoupling performanceVSAvoidpackage footprint
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions capacitor placement from a planar surface-mount approach to a three-dimensional embedded structure within the molding compound. Capacitor plates are positioned vertically within trenches etched into the mold, utilizing the Z-dimension (depth) rather than only the XY-plane, thereby dramatically reducing the horizontal footprint while maintaining decoupling capacitance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The capacitor structure is nested within the molding compound itself. Trenches are etched into the mold, dielectric material is deposited within these trenches, and capacitor plates are formed inside the dielectric, creating a nested configuration where the capacitor is embedded within the package structure rather than sitting on the surface.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If conventional surface-mount capacitors are used, then decoupling function is provided, but routing density is reduced due to limited placement options

Engineering Contradiction:
Improvedecoupling functionVSAvoidrouting density
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By moving capacitor placement into the vertical dimension within the mold structure, the invention frees up surface area for additional routing and signal traces. The embedded configuration allows signal paths to be routed on the surface without obstruction from surface-mounted capacitors, thereby increasing routing density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Area of stationary object

If capacitor footprint is reduced through embedding, then package area is optimized, but manufacturing complexity increases

Engineering Contradiction:
Improvepackage areaVSAvoidmanufacturing process complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The capacitor structure is built during the molding process itself rather than as a separate post-processing step. Trenches are etched into the mold cavity, dielectric material is deposited, and plates are formed before the final encapsulation, integrating capacitor fabrication into the primary manufacturing flow and reducing overall process complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention merges the capacitor fabrication process with the molding compound encapsulation process. Both the package substrate and the decoupling capacitors are manufactured in the same tooling and process flow, combining what would traditionally be separate operations into a unified manufacturing sequence.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution reduces the footprint of capacitors, increases package routing density, and enhances power integrity by minimizing the impact on signal trace routing and allowing for a fully populated solder BGA, while maintaining effective decoupling performance.

Implementation Method 1

separated by a high-permittivity dielectric material

Methodology Applied
Scientific EffectDielectric permittivity: Dielectric Permittivity

Data Source

PatentUS10998261B2Over-molded IC package with in-mold capacitor
Publication Date: 2021.05.04 INTEL CORP
  • US10998261B2 patent drawing
  • US10998261B2 patent drawing
  • US10998261B2 patent drawing

AI summary

Over-molded IC package assemblies including an in-mold capacitor. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more capacitors are fabricated within the molding compound. The capacitors may include two or more metal plates separated by an intervening dielectric material, all of which are embedded within a trench in the molding compound. Individual ones of the capacitor plates may physically contact a conductive land of the package redistribution layer or package substrate, for example to tie the plates to a ground plane and power plane, or two supply rails, in a decoupling capacitor application.