In-Network Prefix-Scan Acceleration via Logical Tree Mapping

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Solution Overview

Problem

Current software-based prefix-scan operations in distributed systems experience increased latency and jitter, reducing overall efficiency due to the need for multiple passes over a logarithmic tree, and lack priority in load balancing workloads across the system.

Innovation Solution

Implementing a hardware mechanism for prefix-scan operations using a network of multi-threaded core nodes with a logical tree topology, where reductions are performed in flight and prioritized, minimizing data movement and energy consumption through pipelined element-wise operations and dedicated virtual channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If software-based prefix-scan operations are implemented using multiple passes over a logarithmic tree, then the operation can be completed, but latency and jitter increase, reducing overall system efficiency

Engineering Contradiction:
ImprovelatencyVSAvoidsystem efficiency
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The prefix-scan operation is segmented into multiple independent reduction phases that can be executed in parallel across different processor cores. Each core performs local reductions on its assigned data segment, and intermediate results are aggregated through a tree-structured communication pattern, eliminating the need for sequential multiple passes

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-pass sequential software model to a multi-dimensional parallel hardware model where computations occur simultaneously across multiple processor cores and communication stages. The logarithmic tree structure provides a dimensional framework for organizing parallel reductions, achieving O(log n) latency instead of O(n) sequential operations

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If hardware mechanisms are implemented for in-network prefix-scan operations, then latency is reduced and priority is improved, but device complexity increases

Engineering Contradiction:
Improveoperation speedVSAvoidhardware complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The network fabric and switch infrastructure are designed to perform multiple functions: standard data communication, collective operations like prefix-scan, and priority-based scheduling. By making the network infrastructure universal and multi-functional, dedicated hardware for prefix-scan is avoided while still achieving hardware-accelerated performance

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system uses its existing network infrastructure and communication protocols to perform prefix-scan operations without requiring external or specialized hardware assistance. The network fabric services its own computational needs by enabling in-network computation through standard switching and routing mechanisms

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12153932B2Techniques for acceleration of a prefix-scan operation
Publication Date: 2024.11.26 INTEL CORP
  • US12153932B2 patent drawing
  • US12153932B2 patent drawing
  • US12153932B2 patent drawing

AI summary

Examples include techniques for an in-network acceleration of a parallel prefix-scan operation. Examples include configuring registers of a node included in a plurality of nodes on a same semiconductor package. The registers to be configured responsive to receiving an instruction that indicates a logical tree to map to a network topology that includes the node. The instruction associated with a prefix-scan operation to be executed by at least a portion of the plurality of nodes.