In-Package Sequencer for Memory Error Correction and Testing
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Solution Overview
Problem
Conventional memory sub-systems face challenges in efficiently performing error correction and memory testing due to the integration of sequencer components within controllers, leading to increased power consumption, signal integrity issues, and high testing costs, especially when adding new memory components or dealing with diverse memory types.
Innovation Solution
The separation of sequencer components from controllers and integration within the same package as memory components allows for independent error correction and testing operations, utilizing shorter traces for improved signal integrity and reduced power consumption, and includes a memory test engine for cost-effective testing of various memory types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sequencer components are integrated within controllers, then device complexity is reduced, but power consumption increases and signal integrity deteriorates
Solution Approach 1:
The patent divides the memory sub-system into separate functional components: the controller handles host communication while the sequencer is extracted and integrated with memory components in a separate package. This segmentation allows the sequencer to operate closer to the memory die, reducing transmission distance and power consumption while maintaining modular design benefits.
Solution Approach 2:
The sequencer component is extracted from the controller package and integrated into a separate package with the memory component. This extraction eliminates the need for long trace connections between controller and memory, thereby reducing power consumption and improving signal integrity while keeping the overall system modular.
2Device complexity
If sequencer components are integrated within controllers, then device complexity is reduced, but signal integrity deteriorates
Solution Approach 1:
The sequencer is extracted from the controller and co-packaged with the memory component, placing it physically closer to the memory die. This extraction shortens the trace length for data transmissions, reducing signal degradation and improving signal integrity while maintaining system modularity.
Solution Approach 2:
The patent changes the spatial arrangement by moving the sequencer from a separate controller package to a co-packaged position adjacent to the memory die. This dimensional repositioning reduces the transmission path length and improves signal integrity without increasing overall system complexity.
3Manufacturing precision
If conventional testing methods are used for diverse memory types, then manufacturing precision is maintained, but testing costs increase
Solution Approach 1:
The memory test engine integrated in the sequencer package is designed to support multiple memory types (e.g., DDR3, DDR4, LPDDR) through a single unified testing platform. This universal testing capability eliminates the need for separate dedicated testing boards for each memory type, reducing testing costs while maintaining manufacturing precision through programmable test patterns.
Solution Approach 2:
Instead of using expensive dedicated physical testing boards for each memory type, the patent implements a software-based memory test engine that can be programmed with different test patterns for various memory types. This virtual copying of testing functionality across multiple memory types reduces hardware costs while maintaining testing accuracy.
Data Source
AI summary
A sequencer component residing in a first package receives data from a controller residing in a second package that is different than the first package including the sequencer component. The sequencer component performs an error correction operation on the data received from the controller. The error correction operation encodes the data with additional data to generate a code word. The sequencer component stores the code word at a memory device.