Apparatus and methods for in-place read refresh for nonvolatile memory devices
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Solution Overview
Problem
Conventional non-volatile memory devices face challenges in achieving high bandwidth and low power consumption, making them unsuitable alternatives to volatile DRAM memory devices for applications requiring rapid data access and storage.
Innovation Solution
The development of high bandwidth flash (HBF) packages that operate at very high bandwidth and low power consumption, with a mechanism to automatically refresh data in-place to mitigate read disturb without erasing, by programming memory cells to higher threshold voltages and adjusting reference voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional NAND memory devices are used, then cost is reduced compared to DRAM, but bandwidth is too low and power consumption is too high
Solution Approach 1:
The patent changes the threshold voltage parameter of memory cells dynamically. During read operations, threshold voltages are increased to create larger margins and prevent read disturb. This parameter adjustment enables nonvolatile memory to achieve higher effective bandwidth while maintaining low power consumption, making it competitive with DRAM for specific applications.
2Quantity of substance
If conventional NAND memory devices are used, then cost is reduced compared to DRAM, but power consumption is too high
Solution Approach 1:
The patent dynamically adjusts the threshold voltage parameter based on read cycle count. When read disturb is detected (after exceeding a threshold number of reads), the system increases threshold voltages to prevent further degradation. This selective parameter adjustment reduces unnecessary power consumption while maintaining data integrity, enabling nonvolatile memory to achieve power consumption levels suitable for replacing DRAM in specific workloads.
3Speed
If memory cells are read repeatedly, then data access speed is improved, but read disturb occurs causing data degradation
Solution Approach 1:
The patent implements a feedback mechanism that monitors read cycle counts and detects when read disturb begins to occur. Based on this feedback, the system automatically adjusts threshold voltages to prevent further data degradation. This closed-loop control enables the memory to maintain both high read speed and data integrity by adapting to the actual state of the memory cells.
Solution Approach 2:
The patent performs preliminary detection of read disturb conditions by monitoring read cycle counts before significant data degradation occurs. When the threshold is exceeded, the system proactively increases threshold voltages to prevent read disturb from compromising data integrity. This preliminary action allows the memory to maintain reliability while continuing to operate at high read speeds.
4Reliability
If threshold voltage margin is increased to prevent read disturb, then data reliability is improved, but read performance decreases
Solution Approach 1:
The patent makes the threshold voltage parameter dynamic rather than static. Threshold voltages are adjusted based on the actual read cycle count and detected read disturb conditions. This dynamic adjustment allows the memory to optimize between read performance and data reliability in real-time, maintaining high read performance when possible while ensuring data integrity when read disturb occurs.
Data Source
AI summary
The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The memory cells are programmed to one bit per memory cell with each memory cell being either in an erased data state or a programmed data state. The memory device also includes circuitry that is configured to determine that the memory cells have experienced significant of read disturb. Without erasing the memory cells, the circuitry is further configured to program the memory cells in the programmed data state directly to higher threshold voltages to increase a threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state.