In-Situ Memory Computing via Row Buffer Serial Transfer
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Solution Overview
Problem
Current in-situ approaches in electronic memory systems are limited in supporting operations like 32-bit addition and multiplication, and are inefficient for data movement, especially in memory-intensive applications such as data analytics and machine learning, due to high energy consumption and execution time.
Innovation Solution
The implementation of memory devices with in-situ computing capabilities using sequential access to row-buffered data, where data is latched in row buffer circuits and serially transferred to an arithmetic logic unit (ALU) for processing, allowing for 32-bit operations and reducing data movement costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data is moved from memory to processor for computation, then computation can be performed, but energy consumption and execution time increase due to high data movement cost
Solution Approach 1:
The patent merges the memory function and computation function into a single integrated structure. Row buffer circuits are placed adjacent to memory cell arrays on the same semiconductor die, and arithmetic logic units are integrated with the row buffers. This allows data to be processed in-situ within the memory device, eliminating the need to move data between separate memory and processor components, thereby reducing both energy consumption and execution time.
Solution Approach 2:
The row buffer circuits serve as an intermediary structure between the memory cell arrays and the arithmetic logic units. Data is first read from memory cells into the row buffer circuits, which then serially transfer the data to the ALU for processing. This intermediary buffer enables efficient data staging and serial transfer, reducing the overall data movement cost while enabling computation.
2Use of energy by moving object
If in-situ processing is implemented in memory, then data movement cost is reduced, but operational versatility is limited to row-wide operations
Solution Approach 1:
The patent implements dynamic data transfer mechanisms where the row buffer circuits can serially transfer data to the ALU in a controlled manner. The system can dynamically select which data to transfer and when, enabling operations beyond simple row-wide operations. The serial transfer capability allows for selective data processing, data dependency handling, and support for various computational operations including 32-bit addition and multiplication.
Solution Approach 2:
The patent segments the data processing into multiple stages: data is read from memory cells, staged in row buffer circuits, then serially transferred to the ALU for processing. This segmentation allows for flexible data handling and enables complex operations by breaking them down into manageable steps, thereby increasing operational versatility while maintaining the benefits of in-situ processing.
3Adaptability or versatility
If row buffer circuits are integrated adjacent to memory cells, then in-situ computing is enabled, but device complexity increases
Solution Approach 1:
The row buffer circuits are designed to serve multiple functions: they act as data storage buffers during read operations, serve as data staging areas for serial transfer to the ALU, and enable in-situ computing operations. The arithmetic logic units are similarly multi-functional, handling various computational operations. This multi-functionality reduces the need for separate dedicated components, thereby managing device complexity while enabling in-situ computing capabilities.
Data Source
AI summary
A method of processing data in a memory can include accessing an array of memory cells located on a semiconductor memory die to provide a row of data including n bits, latching the n bits in one or more row buffer circuits adjacent to the array of memory cells on the semiconductor memory die to provide latched n bits operatively coupled to a column address selection circuit on the semiconductor memory die to provide a portion of the n latched bits as data output from the semiconductor memory die responsive to a memory read operation, and serially transferring the latched n bits in the row buffer circuit to an arithmetic logic unit (ALU) circuit located adjacent to the row buffer circuit on the semiconductor memory die.