In-Storage Logic Hardware Accelerator for Memory
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Solution Overview
Problem
Current semiconductor memory devices face limitations in performing in-storage logic operations efficiently, particularly in minimizing data movement and reducing die area requirements for performing Boolean logic operations.
Innovation Solution
The implementation of a hardware accelerator that includes a memory array with memory cell transistors and a programmable sense amplifier, allowing for the performance of Boolean logic operations directly within the memory cells, minimizing data movement and reducing the number of transistors required compared to standard CMOS implementations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is moved from memory to processor for logic operations, then computation can be performed, but data movement overhead increases and die area increases
Solution Approach 1:
The patent merges the memory array with logic operation circuits, allowing Boolean logic operations to be performed directly within the memory device. This integration eliminates the need to move data between separate memory and processor components, thereby reducing data movement overhead and energy loss while maintaining computation capability.
Solution Approach 2:
The memory device is designed to perform multiple functions: it can store data in the memory array and simultaneously perform logic operations on that data using integrated logic circuits. This multi-functionality allows the same hardware structure to handle both data storage and data processing, improving efficiency without requiring additional data movement.
2Adaptability or versatility
If standard CMOS implementation is used for logic operations, then Boolean logic can be performed, but the number of transistors required increases die area
Solution Approach 1:
The patent combines memory cell transistors with logic operation circuits in a single integrated structure. By merging the functions of data storage and logic operations into the same hardware architecture, the patent reduces the total number of transistors needed compared to separate CMOS logic implementations, thereby reducing die area while maintaining full Boolean logic capability.
3Loss of energy
If in-storage logic operations are implemented, then data movement is minimized, but device complexity increases
Solution Approach 1:
The memory device is designed with multi-functional circuits that can perform both data storage and logic operations. This universal design allows the same hardware structure to handle multiple tasks, reducing the need for additional complex components while minimizing data movement between separate functional blocks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient in-storage logic operations with reduced die area and minimized data movement, enhancing the performance and capacity of semiconductor memory devices.
Implementation Method 1
The amount of charge on the floating gate is typically controlled using Fowler-Nordheim (F-N) tunneling or hot-electron injection.
Implementation Method 2
The amount of charge on the floating gate is typically controlled using Fowler-Nordheim (F-N) tunneling or hot-electron injection.
Implementation Method 3
a sense amplifier in communication with the memory cell transistor and the control circuit. The control circuit configured to acquire a first operand and a second operand for a logic operation
Data Source
AI summary
Systems and methods for performing in-storage logic operations using one or more memory cell transistors and a programmable sense amplifier are described. The logic operations may comprise basic Boolean logic operations (e.g., OR and AND operations) or secondary Boolean logic operations (e.g., XOR and IMP operations). The one or more memory cell transistors may be used for storing user data during a first time period and then used for performing a logic operation during a second time period subsequent to the first time period. During the logic operation, a first memory cell transistor of the one or more memory cell transistors may be programmed with a threshold voltage that corresponds with a first input operand value and then a gate voltage bias may be applied to the first memory cell transistor during the logic operation that corresponds with a second input operand value.