In-Tier Access Line Drivers for Denser 3D Memory Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing three-dimensional (3D) DRAM devices face challenges in increasing memory cell density and optimizing power usage due to limitations in the design and integration of access line drivers, particularly in the arrangement of word lines and sub-access line drivers.
Innovation Solution
The integration of sub-access line drivers (SWDs) within the memory array tiers, utilizing a two-transistor structure comprising NMOS transistors, and a staircase contact arrangement that reduces the physical footprint and enhances signal control, allowing for increased memory cell density and improved power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If sub-access line drivers are integrated within memory array tiers using a two-transistor structure, then memory cell density increases by up to 16-20%, but device complexity increases due to additional transistor integration
Solution Approach 1:
The patent merges the sub-access line driver functionality directly into the memory array tier structure by integrating two-transistor units that combine the driver circuit with the access line control. This consolidation allows the driver to be embedded within the array itself rather than being a separate external component, thereby increasing memory cell density while managing the complexity through functional integration.
Solution Approach 2:
The driver circuit is segmented into discrete two-transistor units that can be independently integrated into each memory tier. Each unit consists of specific transistor configurations (including NMOS and PMOS transistors) that work together to control access lines, allowing modular integration that increases density without proportionally increasing overall device complexity.
2Loss of energy
If sub-access line drivers are embedded in memory array tiers, then power consumption is reduced by minimizing gate-induced drain leakage, but manufacturing complexity increases due to additional fabrication masks
Solution Approach 1:
The patent employs parameter changes in transistor configuration and placement to optimize power characteristics. By carefully selecting transistor types (NMOS and PMOS) and their specific arrangements within the two-transistor units, the design minimizes gate-induced drain leakage current, thereby reducing power consumption while maintaining manufacturability through controlled parameter optimization.
3Area of stationary object
If a staircase contact arrangement is used for sub-access line drivers, then physical footprint is reduced and signal control is enhanced, but fabrication complexity increases due to additional masks
Solution Approach 1:
The staircase contact arrangement utilizes multi-dimensional spatial planning by stacking contacts vertically across different tiers while maintaining horizontal connectivity. This three-dimensional contact structure reduces the planar footprint required for driver integration while preserving signal control capabilities, effectively using vertical space to compensate for the added fabrication complexity.
Data Source
AI summary
A variety of applications can include an apparatus having a three-dimensional (3D) memory device with sub-access line drivers to access lines embedded in a memory array of the 3D memory device. A sub-access line driver to an access line to a tier of memory cells of the memory array can include two transistors coupled to each other and the access line. A first transistor of the two transistors can be coupled at one end of the access line and the second transistor of the two transistors can be coupled at the other end of the access.