Inactive Fin Layout in FETs for Tighter Source/Drain Spacing
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Solution Overview
Problem
In advanced semiconductor technology nodes, the scaling of cell dimensions is constrained by layout restrictions on active area spacing and semiconductor fin spacing, which are typically alleviated by inactive fin structures. However, these structures can limit the complexity and density of integrated circuits.
Innovation Solution
The solution involves forming inactive fin structures only between the source/drain epitaxial features, while leaving the active fin structures and overlying gate structures free of inactive fins, thereby improving active area spacing without the constraints imposed by traditional inactive fin placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If inactive fin structures are placed between active fins to alleviate spacing constraints, then active area spacing is improved, but device complexity increases due to additional structural elements
Solution Approach 1:
The patent extracts the inactive fin structures from between the active fins and relocates them to only exist between the source/drain epitaxial features. This separation removes the conflicting structural elements from the active fin region while maintaining their beneficial spacing effect in the source/drain region, thereby improving active area spacing without unnecessarily increasing device complexity.
Solution Approach 2:
The patent applies local quality by making the presence of inactive fin structures location-dependent: they are present between source/drain epitaxial features where they provide spacing benefits, but absent between active fins where they would increase complexity. This selective placement optimizes the structure for different functional regions of the device.
2Reliability
If inactive fin structures are used to prevent bridging between epitaxial features, then reliability is improved, but manufacturing precision requirements increase due to tighter spacing constraints
Solution Approach 1:
The patent extracts inactive fin structures from the region between active fins and relocates them exclusively to the region between source/drain epitaxial features. This removes the source of manufacturing precision conflicts while preserving the bridging prevention function where it is most needed for reliability.
Data Source
AI summary
A device includes a substrate, a first stack of semiconductor nanostructures vertically overlying the substrate, and a gate structure surrounding the semiconductor nanostructures and abutting an upper side and first and second lateral sides of the first stack. A first epitaxial region laterally abuts a third lateral side of the first stack, and a second epitaxial region laterally abuts a fourth lateral side of the first stack. A first inactive fin laterally abuts the first epitaxial region, and a second inactive fin laterally abuts the second epitaxial region and is physically separated from the first inactive fin by the gate structure.