Semiconductor Package Structure With Inactive Via Carriers

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Solution Overview

Problem

Semiconductor electronic devices face challenges in scaling down while maintaining electrical characteristics, quality, cost, and yield, as single semiconductor chips struggle to meet multifunctional and high-volume data processing needs, necessitating enhanced integration levels.

Innovation Solution

A package structure incorporating a first molded structure with semiconductor devices and inactive elements, encapsulated by an encapsulant, and connected via redistribution structures through vertical conduction paths provided by through vias in inactive elements, allowing for efficient signal transmission without requiring through vias in semiconductor devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple semiconductor chips are integrated to meet multifunctional data processing needs, then functional capability and data processing volume are improved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:

Improvefunctional capabilityVSAvoidintegration complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The package structure is divided into multiple molded structures, each containing semiconductor devices and inactive elements. This segmentation allows independent fabrication and testing of individual modules before final assembly, reducing overall manufacturing complexity while achieving multifunctional integration.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Inactive elements with through vias serve as intermediary components between semiconductor devices and redistribution structures. These inactive elements provide mechanical support and electrical connection pathways without containing active circuitry, simplifying the overall device architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If through vias are formed in semiconductor devices to provide vertical conduction paths, then electrical connectivity is improved, but manufacturing precision requirements and device complexity increase

Engineering Contradiction:

Improveelectrical connectivityVSAvoidvia formation precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

Through vias are formed in inactive elements rather than in active semiconductor devices. The inactive elements act as intermediary carriers that provide the vertical conduction paths needed for electrical connectivity without compromising the integrity or manufacturing simplicity of the active semiconductor devices.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

Instead of forming through vias in the active semiconductor devices (the conventional approach), the patent inverts the approach by forming through vias in the inactive elements. This reversal maintains electrical connectivity functionality while avoiding the manufacturing complexity and precision requirements associated with via formation in active devices.

Inventive Principle:

Principle #13The other way round (Inversion)

3Length of moving object

If semiconductor device dimensions are reduced to meet scaling demands, then device size is improved, but electrical characteristics and manufacturing yield deteriorate

Engineering Contradiction:

Improvedevice sizeVSAvoidelectrical characteristics

Core Design Contradiction:

Length of moving objectVSReliability

Solution Approach 1:

The patent transitions from planar integration to three-dimensional vertical integration by stacking multiple molded structures with inactive elements providing vertical conduction paths. This dimensional change allows continued scaling of individual semiconductor devices while maintaining electrical characteristics through improved signal transmission pathways in the vertical dimension.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250285982A1Package structure including inactive element, assembly structure and method of manufacturing the same

Publication Date: 2025.09.11 NAN YA TECH

AI summary

A package structure, an assembly structure and a manufacturing method are provided. The package structure includes at least one semiconductor device, at least one inactive element and an encapsulant. The at least one inactive element is disposed around the at least one semiconductor device, and includes a main portion and at least one through via extending through the main portion. The encapsulant encapsulates the at least one semiconductor device and the at least one inactive element. A first surface of the encapsulant is substantially coplanar with a first surface of the at least one inactive element and a first surface of the at least one semiconductor device. A second surface of the encapsulant is substantially coplanar with a second surface of the at least one inactive element and a second surface of the at least one semiconductor device.