InAlGaN Nucleation Layer for SiC Substrate Crystallinity
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Solution Overview
Problem
Current semiconductor device structures face challenges in achieving high crystallinity, reducing leakage currents due to threading dislocations, and minimizing thermal boundary resistance, particularly in high electron mobility transistors (HEMTs) using indium aluminum gallium nitride (InxAlyGa1-x-yN) on silicon carbide (SiC) substrates.
Innovation Solution
A semiconductor device structure is developed with a SiC substrate, an Inx1Aly1Ga1-x1-y1N buffer layer, and an Inx2Aly2Ga1-x2-y2N nucleation layer, where x1 and x2, y1 and y2 range from 0 to 1, with specific compositional preferences, to enhance crystallinity and reduce dislocation density, featuring rocking curve peak widths below 250 and 200 arcsec respectively, and a method involving substrate pretreatment and controlled growth conditions to achieve improved crystalline quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an AlN nucleation layer is used to wet SiC substrate surface, then two-dimensional nucleation is achieved and lattice mismatch is compensated, but crystallinity of the nucleation layer and buffer layer is limited
Solution Approach 1:
The patent changes the compositional parameters of the nucleation layer from pure AlN to InxAlyGa1-x-yN with specific In and Al content ranges. This parameter change enables better lattice matching with SiC substrate while maintaining two-dimensional nucleation, resulting in reduced threading dislocation density and improved crystallinity of subsequent buffer layers.
Solution Approach 2:
The patent uses a composite InxAlyGa1-x-yN nucleation layer that combines multiple elements (In, Al, Ga, N) to achieve properties that single-element compounds cannot provide. The composite structure allows simultaneous optimization of lattice matching, thermal conductivity, and nucleation characteristics, thereby improving overall device quality.
2Temperature
If heteroepitaxial growth is performed on SiC substrate, then high thermal conductivity is achieved, but thermal boundary resistance remains high
Solution Approach 1:
The patent optimizes compositional parameters of the nucleation layer (InxAl1-xN with specific x ranges) to improve interface quality between SiC substrate and buffer layer. This parameter optimization reduces thermal boundary resistance while preserving the high thermal conductivity of the SiC substrate, enabling more efficient heat extraction.
3Reliability
If InxAlyGa1-x-yN layers are grown on SiC, then high electron mobility is achieved, but leakage current due to threading dislocations increases
Solution Approach 1:
The patent performs preliminary action by creating a high-quality InxAlyGa1-x-yN nucleation layer with controlled composition before growing the main device layers. This preliminary nucleation layer serves as a template that minimizes threading dislocation generation, thereby reducing leakage current paths while enabling high electron mobility in subsequent AlGaN/GaN heterostructures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure exhibits enhanced crystallinity, reduced leakage currents, and lower thermal boundary resistance compared to prior art, with improved coalescence and reduced oxygen and carbon contamination, leading to better performance in HEMTs.
Implementation Method 1
an aluminum nitride (AlN) nucleation layer is used to wet SiC substrate surface for two-dimensional nucleation process and to compensate for the lattice mismatch
Implementation Method 2
as determined by X-ray Diffraction (XRD)
Data Source
AI summary
The present document discloses a semiconductor device structure (1) comprising a SiC substrate (11), an Inx1Aly1Ga1-x1-y1N buffer layer (13), wherein x1=0-1, y1=0-1 and x1+y1=1, and an Inx2Aly2Ga1-x2-y2N nucleation layer (12), wherein x2=0-1, y2=0-1 and x2+y2=1, sandwiched between the SiC substrate (11) and the buffer layer (13). The buffer layer (13) presents a rocking curve with a (102) peak having a FWHM below 250 arcsec, and the nucleation layer (12) presents a rocking curve with a (105) peak having a FWHM below 200 arcsec, as determined by X-ray Diffraction (XRD).Methods of making such a semiconductor device structure are disclosed.