InAlN Semiconductor Device In Elimination Prevention
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Solution Overview
Problem
InAlN-based semiconductor devices face challenges during high-temperature manufacturing processes, where Indium (In) is prone to elimination, leading to reduced device characteristics and increased on-resistance.
Innovation Solution
A semiconductor device structure incorporating an InAlN electron supply layer with n-type regions formed by ion implantation and a heat-protective SiN film, followed by Si-activation annealing, to prevent In elimination and maintain device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If high-temperature heating process is performed during manufacturing, then device manufacturing can be completed, but Indium (In) is eliminated from the InAlN electron supply layer, leading to reduced device characteristics and increased on-resistance
Solution Approach 1:
An upper surface layer made of nitride semiconductor material (AlN, GaN, or InGaN) is introduced as an intermediary protective layer between the InAlN electron supply layer and the high-temperature processing environment. This upper surface layer acts as a barrier that prevents Indium elimination during subsequent high-temperature manufacturing steps such as silicon activation annealing, while still allowing the manufacturing process to proceed. The upper surface layer is formed after the InAlN layer and has a composition that is more resistant to Indium loss at high temperatures.
2Reliability
If InAlN is used as electron supply layer, then greater 2DEG generation and lower on-resistance are achieved, but Indium elimination occurs during high-temperature processing, worsening device characteristics
Solution Approach 1:
The upper surface layer is formed in advance before any high-temperature processing steps are performed. This preliminary formation of the protective upper surface layer ensures that when subsequent high-temperature processes (such as silicon activation annealing at 700-900°C) are conducted, the Indium in the InAlN electron supply layer is already protected from elimination. The upper surface layer is deposited using techniques such as MOCVD, MBE, or sputtering, and its formation is completed before any thermal processing that could cause Indium loss.
3Reliability
If n-type regions are formed by ion implantation to lower contact resistance, then source and drain contact resistance is reduced, but additional manufacturing steps and complexity are introduced
Solution Approach 1:
The formation of n-type regions through ion implantation is merged with the existing manufacturing process flow. The ion implantation step is performed after the upper surface layer is formed and before final device completion, combining the contact resistance reduction function with the standard fabrication sequence. This integration allows the additional functionality to be added without significantly increasing overall process complexity, as the ion implantation can be performed using standard semiconductor manufacturing equipment and is incorporated into the existing process architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively lowers contact resistance and maintains the high 2DEG generation, thereby improving the on-resistance and overall characteristics of the semiconductor device.
Implementation Method 1
a heat-protective SiN film to be formed on the upper surface layer; followed by Si-activation annealing
Implementation Method 2
n-type regions to be formed in the upper surface layer and the electron supply layer immediately below regions where the source electrode and the drain electrode are formed
Implementation Method 3
followed by Si-activation annealing
Data Source
AI summary
A semiconductor device includes an electron transit layer configured to be formed on a substrate; an electron supply layer configured to be formed on the electron transit layer; an upper surface layer configured to be formed on the electron supply layer; a gate electrode configured to be formed on the electron supply layer or the upper surface layer; a source electrode and a drain electrode configured to be formed on the upper surface layer; and first conductivity-type regions configured to be formed in the upper surface layer and the electron supply layer immediately below regions where the source electrode and the drain electrode are formed. The electron supply layer is formed of a nitride semiconductor including In. The upper surface layer is formed of a material including a nitride of one or more elements selected among B, Al, and Ga.