In-band SPI Bit Error Detection and Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High system failures in non-volatile memory products due to serial peripheral interface (SPI) flash issues result in significant costs, with no standard mechanism to detect flash bit errors, leading to random and unpredictable system failures.
Innovation Solution
In-band detection and correction of bit errors are achieved through a serial bus controller linked to a memory controller, using error correction code (ECC) generation and reporting on existing SPI bus lines, allowing for real-time error detection and correction without additional pins, enabling the host device to correct bit errors over the in-band link.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If no error detection mechanism is implemented, then device complexity is reduced, but system reliability deteriorates due to random bit errors causing system failures
Solution Approach 1:
The patent merges error detection and correction functionality into the existing SPI bus infrastructure by utilizing idle time slots within the same communication channel. The host device sends read commands and receives data through the SPI bus, and error detection/correction operations are performed during the same bus transaction without requiring separate dedicated error detection hardware or additional communication channels. This combining approach improves reliability while avoiding the complexity of separate error detection systems.
Solution Approach 2:
The SPI bus is made multi-functional by enabling it to serve both data transmission and error detection purposes. The same SPI bus lines (SCK, MOSI, MISO, CS) that carry normal data traffic are also used to convey error status information and correction commands. The host device performs universal operations including normal read/write commands, error detection through read-verify cycles, and correction through program-verify cycles, all through the same SPI interface without requiring dedicated error detection pins or channels.
2Measurement precision
If additional pins are added for error detection, then measurement precision of bit errors is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines error detection functionality with the existing SPI bus lines, eliminating the need for additional dedicated error detection pins. The same MISO line that returns data to the host is also used to return error status information. The same MOSI line that sends commands is used to send correction commands. This merging of functions achieves precise bit error detection without adding any physical pins or increasing chipset complexity.
Solution Approach 2:
The SPI bus lines are designed to be universal, serving multiple functions including data transmission, error status reporting, and correction command delivery. The CS (chip select) line universally controls both normal operations and error detection sequences. The FDO (flash device output) signal universally indicates both data readiness and error conditions. This multi-functionality allows precise error detection while maintaining the original pin count and avoiding additional manufacturing complexity.
3Reliability
If real-time error detection is implemented, then system reliability is improved, but loss of time due to additional verification operations increases
Solution Approach 1:
The patent implements preliminary error detection by performing read-verify operations immediately after write operations complete. The host device sends a read command right after the program or erase operation finishes, allowing detection of errors before they propagate or cause system failures. This preliminary verification catches errors early in the process, improving reliability while minimizing the time penalty since the verification is performed as part of the normal write sequence rather than as a separate delayed operation.
Solution Approach 2:
The system performs periodic error detection through scheduled read-verify operations at regular intervals during normal operation. After each write/erase cycle, the host automatically initiates a read-verify sequence, creating a periodic pattern of error checking. This periodic approach ensures consistent error detection coverage while optimizing the timing to occur during naturally occurring bus idle periods, thereby minimizing the impact on overall system performance and avoiding continuous monitoring overhead.
Data Source
AI summary
Embodiments include a serial bus controller that may be coupled to an in band serial peripheral interface (SPI) link, to request a write of data and a subsequent read of the data from a memory device and in response to the request to read the data, receive a bit error report and optionally correct the bit error over the in band SPI link. Embodiments include a memory device, e.g., a flash memory device, to detect and report the bit error over the in band SPI link, where the flash memory device, in response to a request to write and/or erase data, calculates or determines an error correction code (ECC) and stores corresponding parity data. In embodiments, after receiving a subsequent request to read the data, the flash memory device accesses the stored parity data to check the ECC for a bit error and if a bit error is detected, reports the detected bit error over the in band SPI link. Other embodiments may be described and claimed.