3D Semiconductor Devices With Inclined Gate Electrodes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional semiconductor devices face challenges in achieving high reliability and reducing manufacturing costs, particularly in the fine pattern formation processes required for high integration density, which often necessitate expensive equipment.
Innovation Solution
The design incorporates a substrate with a cell array region, a contact region, and a peripheral circuit region, featuring a stack structure with gate electrodes and vertical structures, along with cell contact plugs that connect to the gate electrodes, where the upper surfaces of the gate electrodes have acute angles relative to the substrate surface, allowing for improved connectivity and reduced manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional semiconductor devices are designed to achieve high integration density, then manufacturing cost per bit is reduced, but manufacturing complexity and processing difficulty increase
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertical structures by forming gate electrodes and contact plugs in multiple stacked layers. This dimensional change enables higher integration density by utilizing vertical space rather than only horizontal area, allowing more memory cells to be packed into the same footprint while maintaining manufacturability through standardized 3D fabrication processes
2Manufacturing precision
If fine pattern formation techniques are used to increase integration density, then device performance improves, but manufacturing cost increases due to expensive equipment requirements
Solution Approach 1:
The patent divides the semiconductor device into distinct functional regions including cell array regions with high-density memory cells and contact regions with simplified structures. This segmentation allows different manufacturing precision requirements to be applied to different areas, enabling fine pattern formation only where necessary in the cell arrays while using less complex, lower-cost processes in the contact regions, thereby reducing overall manufacturing cost
3Ease of manufacture
If conventional horizontal contact structures are used, then manufacturing is simpler, but connectivity and signal transmission efficiency are limited
Solution Approach 1:
The patent forms contact plugs that extend vertically through multiple stacked gate electrode layers rather than only horizontally. This vertical dimensionality enables direct electrical connection between upper and lower memory cell layers, significantly improving signal transmission efficiency and device reliability while maintaining manufacturing feasibility through vertical etching and filling processes
Data Source
AI summary
A three-dimensional semiconductor device includes a substrate including a cell array region and a contact region, a stack structure including gate electrodes sequentially stacked on the substrate, vertical structures penetrating the stack structure, and cell contact plugs connected to end portions of the gate electrodes in the contact region. Upper surfaces of the end portions of the gate electrodes have an acute angle with respect to an upper surface of the substrate in the cell array region.